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AT83C24NDS-TIRIL Datasheet(PDF) 11 Page - ATMEL Corporation |
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AT83C24NDS-TIRIL Datasheet(HTML) 11 Page - ATMEL Corporation |
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11 / 42 page  11 AT83C24 4234E–SCR–09/04 CIO, CC4, CC8 Controller The CIO, CC4, CC8 output pins are driven respectively by CARDIO, CARDC4, CARDC8 bits values or by I/O, C4, C8 signal pins. This selection depends of the IODIS bit value. If IODIS is reset, data are bidirectional between respectively I/O, C4, C8 pins and CIO, CC4, CC8 pins. Figure 5. CIO, CC4, CC8 Block Diagram IO and CIO pins are linked together through the on chip level shifters if IODIS bit=0 in INTERFACE register. This is done automatically during an hardware activation. Their iddle level are 1. With IO high, CIO is pulled up. The same behavior is applicable on C4/ CC4 and C8/ CC8 pins. The maximum frequency on those lines depends on CLK frequency (3 clock rising edges to transfer). With CLK=27MHz, the maximum frequency on this line is 1.5MHz. Due to the minimum transfer delay allowed for NDS applications, the CLK minimum fre- quency is 18MHz. Clock Controller The clock controller generates two clocks (as shown in Figure 6 and Figure 7): 1. a clock for the CCLK: Four different sources can be used: CLK pin, DCCLK sig- nal, CARDCK bit or A2/CK pin (in transparent mode). 2. a clock for DC/DC converter. CIO 0 1 0 1 CARDIO bit CC4 CC8 0 1 CARDC8 bit IODIS bit CARDC4 bit I/O C4 C8 CVCC CVCC CVCC EVCC EVCC |
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