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NP60N06PDK-E2-AY Datasheet(PDF) 3 Page - Renesas Technology Corp |
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NP60N06PDK-E2-AY Datasheet(HTML) 3 Page - Renesas Technology Corp |
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3 / 9 page  NP60N06PDK R07DS1296EJ0101 Rev.1.01 Page 3 of 7 Dec 21, 2015 Electrical Characteristics (TA = 25°C) Item Symbol Min Typ Max Unit Test Conditions Zero Gate Voltage Drain Current IDSS 1 μA VDS = 60 V, VGS = 0 V Gate Leakage Current IGSS ±100 nA VGS = ±20 V, VDS = 0 V Gate to Source Threshold Voltage VGS(th) 1.5 2.1 2.5 V VDS = VGS, ID = 250 μA Forward Transfer Admittance ∗ 1 | yfs | 30 54 S VDS = 5 V, ID = 30 A Drain to Source On-state Resistance ∗ 1 RDS(on)1 6.4 7.9 m Ω VGS = 10 V, ID = 30 A RDS(on)2 7.0 12.0 m Ω VGS = 4.5 V, ID = 15 A Input Capacitance Ciss 2400 3600 pF VDS = 25 V, VGS = 0 V, f = 1 MHz Output Capacitance Coss 230 350 pF Reverse Transfer Capacitance Crss 80 150 pF Turn-on Delay Time td(on) 18 40 ns VDD = 30 V, ID = 30 A, VGS = 10 V, RG = 0 Ω Rise Time tr 6 20 ns Turn-off Delay Time td(off) 45 90 ns Fall Time tf 3 10 ns Total Gate Charge QG 37 56 nC VDD = 48 V, VGS = 10 V, ID = 60 A Gate to Source Charge QGS 9 nC Gate to Drain Charge QGD 8 nC Body Diode Forward Voltage ∗ 1 VF(S-D) 0.9 1.5 V IF = 60 A, VGS = 0 V Reverse Recovery Time trr 32 ns IF = 60 A, VGS = 0 V, di/dt = 100 A/ μs Reverse Recovery Charge Qrr 30 nC Note: *1. Pulsed test TEST CIRCUIT 3 GATE CHARGE VGS = 20 → 0 V PG. RG = 25 Ω 50 Ω D.U.T. L VDD TEST CIRCUIT 1 AVALANCHE CAPABILITY PG. D.U.T. RL VDD TEST CIRCUIT 2 SWITCHING TIME RG PG. IG = 2 mA 50 Ω D.U.T. RL VDD ID VDD IAS VDS BVDSS Starting Tch VGS 0 Duty Cycle ≤ 1% τ = 1 μs τ VGS Wave Form VDS Wave Form VGS VDS 10% 0 0 90% 90% 90% VGS V DS ton toff td(on) tr td(off) tf 10% 10% |
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