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COP87L88GG Datasheet(PDF) 5 Page - National Semiconductor (TI) |
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COP87L88GG Datasheet(HTML) 5 Page - National Semiconductor (TI) |
5 / 42 page AC Electrical Characteristics b40 C s TA s a85 C unless otherwise specified Parameter Conditions Min Typ Max Units Instruction Cycle Time (tc) Crystal Resonator 27V s VCC s 45V 25 DC m s 45V s VCC s 55V 1 DC m s RC Oscillator 27V s VCC s 45V 75 DC m s 45V s VCC s 55V 3 DC m s Inputs tSETUP 45V s VCC s 55V 200 ns 27V s VCC s 45V 500 ns tHOLD 45V s VCC s 55V 60 ns 27V s VCC s 45V 150 ns Output Propagation Delay (Note 6) RL e 22k CL e 100 pF tPD1 tPD0 SO SK 45V s VCC s 55V 07 m s 27V s VCC s 45V 175 m s All Others 45V s VCC s 55V 10 m s 27V s VCC s 45V 25 m s MICROWIRE Setup Time (tUWS)VCC t 45V 20 ns MICROWIRE Hold Time (tUWH)VCC t 45V 56 ns MICROWIRE Output Propagation Delay (tUPD)VCC t 45V 220 ns Input Pulse Width (Note 7) Interrupt Input High Time 10 tc Interrupt Input Low Time 10 tc Timer 1 2 3 Input High Time 10 tc Timer 1 2 3 Input Low Time 10 tc Reset Pulse Width 10 m s tc e Instruction Cycle Time Note 1 Maximum rate of voltage change must be k 05 Vms Note 2 Supply and IDLE currents are measured with CKI driven with a square wave Oscillator CKO driven 180 out of phase with CKI inputs connected to VCC and outputs driven low but not connected to a load Note 3 The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations by bringing CKI high Test Conditions All inputs tied to VCC L and G ports in the TRI-STATE mode and tied to ground all outputs low and tied to ground The clock monitor is disabled Note 4 The user must guarantee that D2 pin does not source more than 10 mA during RESET If D2 sources more than 10 mA during reset the device will go into programming mode Note 5 Pins G6 and RESET are designed with a high voltage input network These pins allow input voltages l VCC and the pins will have sink current to VCC when biased at voltages l VCC (the pins do not have source current when biased at a voltage below VCC) The effective resistance to VCC is 750X (typical) These two pins will not latch up The voltage at the pins must be limited to k 14V WARNING Voltages in excess of 14V will cause damage to the pins This warning excludes ESD transients Note 6 The output propagation delay is referenced to the end of the instruction cycle where the output change occurs Note 7 Parameter characterized but not tested http www nationalcom 5 |
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