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STK12C68-5KF45I Datasheet(PDF) 4 Page - List of Unclassifed Manufacturers

Part No. STK12C68-5KF45I
Description  8K x 8 AutoStore™ nvSRAM QuantumTrap™ CMOS Nonvolatile Static RAM
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STK12C68
October 2003
4
Document Control # ML0008 rev 0.4
SRAM WRITE CYCLES #1 & #2
(VCC = 5.0V ± 10%)e
Note j:
If W is low when E goes low, the outputs remain in the high-impedance state.
Note k: E or W must be
≥ VIH during address transitions.
Note l:
HSB must be high during SRAM WRITE cycles.
SRAM WRITE CYCLE #1: W Controlledk, l
SRAM WRITE CYCLE #2: E Controlledk, l
NO.
SYMBOLS
PARAMETER
STK12C68-25
STK12C68-35
STK12C68-45
STK12C68-55
UNITS
#1
#2
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
12
tAVAV
tAVAV
tWC
Write Cycle Time
25
35
45
55
ns
13
tWLWH
tWLEH
tWP
Write Pulse Width
20
25
30
45
ns
14
tELWH
tELEH
tCW
Chip Enable to End of Write
20
25
30
45
ns
15
tDVWH
tDVEH
tDW
Data Set-up to End of Write
10
12
15
25
ns
16
tWHDX
tEHDX
tDH
Data Hold after End of Write
0000
ns
17
tAVWH
tAVEH
tAW
Address Set-up to End of Write
20
25
30
45
ns
18
tAVWL
tAVEL
tAS
Address Set-up to Start of Write
0000
ns
19
tWHAX
tEHAX
tWR
Address Hold after End of Write
0000
ns
20
tWLQZ i, j
tWZ
Write Enable to Output Disable
10
13
14
15
ns
21
tWHQX
tOW
Output Active after End of Write
5555
ns
PREVIOUS DATA
DATA OUT
E
ADDRESS
12
tAVAV
W
16
tWHDX
DATA IN
19
tWHAX
13
tWLWH
18
tAVWL
17
tAVWH
DATA VALID
20
tWLQZ
15
tDVWH
HIGH IMPEDANCE
21
tWHQX
14
tELWH
DATA OUT
E
ADDRESS
12
tAVAV
W
DATA IN
13
tWLEH
17
tAVEH
DATA VALID
HIGH IMPEDANCE
14
tELEH
18
tAVEL
15
tDVEH
19
tEHAX
16
tEHDX




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