CY7C68013
Document #: 38-08012 Rev. *E
Page 7 of 48
3.11
Register Addresses
3.12
Endpoint RAM
3.12.1
Size
• 3 × 64 bytes
(Endpoints 0 and 1)
• 8 × 512 bytes
(Endpoints 2, 4, 6, 8)
3.12.2
Organization
• EP0
Bidirectional endpoint zero, 64-byte buffer
• EP1IN, EP1OUT
64-byte buffers, bulk or interrupt
• EP2,4,6,8
Eight 512-byte buffers, bulk, interrupt, or isochronous. EP2
and 6 can be either double, triple, or quad buffered. For high-
speed endpoint configuration options, see Figure 3-3.
3.12.3
Set-up Data Buffer
A separate eight-byte buffer at 0xE6B8-0xE6BF holds the
SETUP data from a CONTROL transfer.
3.12.4
Endpoint Configuration (High-speed Mode)
Endpoints 0 and 1 are the same for every configuration.
Endpoint 0 is the only CONTROL endpoint, and endpoint 1 can
be either BULK or INTERRUPT. To the left of the vertical line,
the user may pick different configurations for EP2&4 and
EP6&8, since none of the 512-byte buffers are combined
between these endpoint groups. An example endpoint config-
uration would be:
EP2—1024 double buffered; EP6—512 quad buffered.
To the right of the vertical line, buffers are shared between
EP2–8, and therefore only entire columns may be chosen.
FFFF
F000
E800
E7FF
E7C0
E7BF
E780
E77F
E740
E73F
E700
E6FF
E600
E480
E47F
E400
E3FF
E200
E1FF
E000
E5FF
EFFF
4 kbytes EP2-EP8 buffers
(8 × 512)
2 kbytes RESERVED
64 bytes EP1IN
64 bytes EP1OUT
64 bytes EP0 IN/OUT
64 bytes RESERVED
256 bytes Registers
384 bytes RESERVED
128 bytes GPIF Waveforms
512 bytes RESERVED
512 bytes
8051 xdata RAM
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