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CY6116A
CY6117A
6116A: 11/8/89
Revision: Monday, November 8, 1993
4
Switching Waveforms
Read Cycle No. 1[10, 11]
ADDRESS
DATA OUT
PREVIOUS DATA VALID
DATA VALID
tRC
tAA
tOHA
6116A-7
Read Cycle No. 2[10, 12]
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
DATA OUT
HIGH IMPEDANCE
IMPEDANCE
ICC
ISB
tHZOE
tHZCE
tPD
OE
CE
HIGH
VCC
SUPPLY
CURRENT
6116A-8
Write Cycle No. 1 (WE Controlled)[9, 13]
tWC
DATA VALID
DATA UNDEFINED
HIGH IMPEDANCE
tSCE
tAW
tSA
tPWE
tHA
tHD
tHZWE
tLZWE
tSD
CE
WE
DATA IN
DATA I/O
ADDRESS
6116A-9
Notes:
10. WE is HIGH for read cycle.
11. Device is continuously selected. OE,CE =VIL.
12. Address valid prior to or coincident with CE transition LOW.
13. Data I/O pins enter highimpedance state, as shown, when OE is held
LOW during write.
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