GM76U256CLLE datasheet(4/11 Pages) HYNIX

Part #	GM76U256CLLE

Description	32K x8 bit 3.0V Low Power CMOS slow SRAM

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Manufacturer	HYNIX [Hynix Semiconductor]

Direct Link	http://www.skhynix.com/kor/main.do

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4 / 11 page

GM76U256C Series

Rev 02 / Apr. 2001

3

DC CHARACTERISTICS

Vcc = 3.0V

±10%, TA = 0°C to 70°C (Normal)/-25°C to 85°C (Extended), unless otherwise specified.

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

ILI

Input Leakage Current

Vss < VIN < Vcc

-1

-

1

uA

ILO

Output Leakage Current

Vss < VOUT < Vcc, /CS = VIH or

/

OE = VIH or /WE = VIL

-1

-

1

uA

Icc

Operating Power Supply

Current

/CS = VIL,

VIN = VIH or VIL, II/O = 0mA

-

2

mA

ICC1

Average Operating Current

/CS = VIL, VIN = VIH or VIL,

Min. Duty Cycle = 100%, II/O = 0mA

-

30

mA

ICC2

Average Operating Current

/CS = VIL, VIN = VIH or VIL,

Cycle = 1us , II/O = 0mA

-

5

mA

ISB

TTL Standby Current

(TTL Inputs)

/CS= VIH,

VIN = VIH or VIL

-

0.3

mA

ISB1

CMOS Standby Current

/CS > Vcc - 0.2V

L

-

20

uA

(CMOS Inputs)

VIN > Vcc - 0.2V or

LL

-

10

uA

VIN < Vss + 0.2V

LE

-

30

uA

LLE

-

15

uA

VOL

Output Low Voltage

IOL = 2.1mA

-

0.4

V

VOH

Output High Voltage

IOH = -1.0mA

2.4

-

V

Note : Typical values are at Vcc =3.0V, TA = 25

°C

AC CHARACTERISTICS(I)

Vcc = 3.0V

±10%, TA = 0°C to 70°C (Normal) / -25°C to 85°C (Extended) unless otherwise specified.

-10

-12

Min.

Max.

Min

Max.

1

tRC

Read Cycle Time

100

-

120

-

ns

2

tAA

Address Access Time

-

100

-

120

ns

3

tACS

Chip Select Access Time

-

100

-

120

ns

4

tOE

Output Enable to Output Valid

-

50

-

60

ns

5

tCLZ

Chip Select to Output in Low Z

10

-

10

-

ns

6

tOLZ

Output Enable to Output in Low Z

5

-

5

-

ns

7

tCHZ

Chip Disable to Output in High Z

0

35

0

40

ns

8

tOHZ

Out Disable to Output in High Z

0

35

0

40

ns

9

tOH

Output Hold from Address Change

15

-

15

-

ns

10

tWC

Write Cycle Time

100

-

120

-

ns

11

tCW

Chip Selection to End of Write

80

-

100

-

ns

12

tAW

Address Valid to End of Write

80

-

100

-

ns

13

tAS

Address Set-up Time

0

-

0

-

ns

14

tWP

Write Pulse Width

70

-

85

-

ns

15

tWR

Write Recovery Time

0

-

0

-

ns

16

tWHZ

Write to Output in High Z

0

30

0

40

ns

17

tDW

Data to Write Time Overlap

40

-

50

-

ns

18

tDH

Data Hold from Write Time

0

-

0

-

ns

19

tOW

Output Active from End of Write

10

-

10

-

ns

READ CYCLE

Symbol

Parameter

#

Unit

WRITE CYCLE

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