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IDT2305-1HDCG Datasheet(PDF) 1 Page - Integrated Device Technology

Part # IDT2305-1HDCG
Description  3.3V ZERO DELAY CLOCK BUFFER
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT2305-1HDCG Datasheet(HTML) 1 Page - Integrated Device Technology

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1
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
IDT2305
3.3VZERODELAYCLOCKBUFFER
DECEMBER 2007
2007
Integrated Device Technology, Inc.
DSC 5174/8
c
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
• Phase-Lock Loop Clock Distribution
• 10MHz to 133MHz operating frequency
• Distributes one clock input to one bank of five outputs
• Zero Input-Output Delay
• Output Skew < 250ps
• Low jitter <200 ps cycle-to-cycle
• IDT2305-1 for Standard Drive
• IDT2305-1H for High Drive
• No external RC network required
• Operates at 3.3V VDD
• Power down mode
• Available in SOIC package
FUNCTIONAL BLOCK DIAGRAM
IDT2305
3.3V ZERO DELAY
CLOCK BUFFER
PLL
8
CLK1
CLK2
CLK3
CLK4
Control
Logic
REF
CLKOUT
1
3
2
5
7
DESCRIPTION:
The IDT2305 is a high-speed phase-lock loop (PLL) clock buffer,
designed to address high-speed clock distribution applications. The zero
delay is achieved by aligning the phase between the incoming clock and
the output clock, operable within the range of 10 to 133MHz.
The IDT2305 is an 8-pin version of the IDT2309. IDT2305 accepts one
reference input, and drives out five low skew clocks. The -1H version of this
device operates, up to 133MHz frequency and has a higher drive than the
-1 device. All parts have on-chip PLLs which lock to an input clock on the
REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT
pad. In the absence of an input clock, the IDT2305 enters power down. In
this mode, the device will draw less than 25μA, the outputs are tri-stated,
and the PLL is not running, resulting in a significant reduction of power.
The IDT2305 is characterized for both Industrial and Commercial
operation.


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