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STK12C68-5L55M Datasheet(PDF) 5 Page - List of Unclassifed Manufacturers

Part No. STK12C68-5L55M
Description  8K x 8 AutoStore™ nvSRAM QuantumTrap™ CMOS Nonvolatile Static RAM
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STK12C68
October 2003
5
Document Control # ML0008 rev 0.4
HARDWARE MODE SELECTION
Note m: HSB STORE operation occurs only if an SRAM WRITE has been done since the last nonvolatile cycle. After the STORE (if any) completes,
the part will go into standby mode, inhibiting all operations until HSB rises.
Note n: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
Note o: I/O state assumes G < VIL. Activation of nonvolatile cycles does not depend on state of G.
HARDWARE STORE CYCLE
(VCC = 5.0V ± 10%)e
Note p: E and G low for output behavior.
Note q: E and G low and W high for output behavior.
Note r:
tRECOVER is only applicable after tSTORE is complete.
HARDWARE STORE CYCLE
E
W
HSB
A12 - A0 (hex)
MODE
I/O
POWER
NOTES
H
X
H
X
Not Selected
Output High Z
Standby
L
H
H
X
Read SRAM
Output Data
Active
o
L
L
H
X
Write SRAM
Input Data
Active
X
X
L
X
Nonvolatile
STORE
Output High Z
lCC
2
m
LH
H
0000
1555
0AAA
1FFF
10F0
0F0F
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
STORE
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
lCC
2
n, o
LH
H
0000
1555
0AAA
1FFF
10F0
0F0E
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
n, o
NO.
SYMBOLS
PARAMETER
STK12C68
UNITS NOTES
Standard
Alternate
MIN
MAX
22
tSTORE
tHLHZ
STORE Cycle Duration
10
ms
i, p
23
tDELAY
tHLQZ
Time Allowed to Complete SRAM Cycle
1
µsi, q
24
tRECOVER
tHHQX
Hardware STORE High to Inhibit Off
700
ns
p, r
25
tHLHX
Hardware STORE Pulse Width
15
ns
26
tHLBL
Hardware STORE Low to Store Busy
300
ns
DATA VALID
HSB (IN)
DATA VALID
25
tHLHX
23
tDELAY
22
tSTORE
24
tRECOVER
HSB (OUT)
HIGH IMPEDANCE
26
tHLBL
HIGH IMPEDANCE
DQ (DATA OUT)




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