________________________________________________________________________

http://www.union-ic.com Rev.01 Jan.2015

9/14

UM805/811/812

Applications Information

In addition to issuing a reset to the µP during power-up, power-down, and brownout conditions, the

Figure 3 shows typical transient duration vs. reset comparator overdrive, for which the

UM805/811/812 do not generate a reset pulse. The graph was generated using a negative-going

indicated (reset comparator overdrive). The graph indicates the typical maximum pulse width a

of the transient increases (goes farther below the reset threshold), the maximum allowable pulse

reset threshold and lasts 40µs or less will not cause a reset pulse to be issued. A 0.1µF capacitor

Figure 3. Maximum Transient Duration without Causing a Reset Pulse

vs. Reset Comparator Overdrive

Ensuring a Valid RESET

______________

_____________

output no longer sinks current—it becomes an open

circuit. Therefore, high-impedance CMOS-logic inputs connected to RESET

_____________

can drift to

undetermined voltages. This presents no problem in most applications since most µP and other

_____________

must be valid

down to 0V, adding a pull-down resistor to RESET

_____________

pin will causes any stray leakage currents to

flow to ground, holding RESET

_____________

low (Figure 4). R1’s value is not critical; 100kΩ is large enough

not to load RESET

_____________

and small enough to pull RESET

_____________

to ground.

UM8_ _LE/ME/JE

UM8_ _TE/SE/RE/ZE