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UM809WP Datasheet(PDF) 6 Page - Union Semiconductor, Inc. |
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UM809WP Datasheet(HTML) 6 Page - Union Semiconductor, Inc. |
6 / 14 page ________________________________________________________________________ http://www.union-ic.com Rev.06 Apr.2015 6/14 UM809/810 Detailed Description A microprocessor’s (µP’s) reset input starts the µP in a known state. The UM809/810 asserts reset to prevent code-execution errors during power-up, power-down, or brownout conditions. They assert a reset signal whenever the VCC supply voltage declines below a preset threshold, keeping it asserted for at least 140ms after VCC has risen above the reset threshold. The UM809/810 has a push-pull output stage. Applications Information VCC Transient Rejection In addition to issuing a reset to the µP during power-up, power-down, and brownout conditions, the UM809/810 is relatively immune to short-duration negative-going VCC transients (glitches). Figure 9 shows typical transient duration vs. reset comparator overdrive, for which the UM809/810 do not generate a reset pulse. The graph was generated using a negative-going pulse applied to VCC, starting 0.5V above the actual reset threshold and ending below it by the magnitude indicated (reset comparator overdrive). The graph indicates the maximum pulse width a negative-going VCC transient can have without causing a reset pulse. As the magnitude of the transient increases (goes farther below the reset threshold), the maximum allowable pulse width decreases. Typically, for the UM8_L and UM8_M, a VCC transient that goes 100mV below the reset threshold and lasts 20µs or less will not cause a reset pulse. A 0.1µF bypass capacitor mounted as close as possible to the VCC pin provides additional transient immunity. VCC VTH Overdrive Duration TA=+25 oC UM8XXL/M/J UM8XXR/S/T 1 10 100 1000 0 80 160 240 320 400 RESET COMPARATOR OVERDRIVE (mV) Figure 9. Maximum Transient Duration vs Overdrive for Glitch Rejection at 25°C Output Signal Integrity during Power-Down When VCC falls below 1V, the UM809 RESET _____________ output no longer sinks current—it becomes an open circuit. Therefore, high-impedance CMOS logic inputs connected to RESET _____________ can drift to undetermined voltages. This presents no problem in most applications since most µP and other circuitry is inoperative with VCC below 1V. However, in applications where RESET _____________ must be valid down to 0V, adding a pull-down resistor to RESET _____________ causes any stray leakage currents to flow to ground, holding RESET _____________ low (Figure 10). R1’s value is not critical; 100kΩ is large |
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