5

Copyright © 2012 Future Technology Devices International Limited

UMFT231XE

Version 1.0

Document Reference No.: FT_000652

Clearance No.: FTDI#

294

4.2

Signal Descriptions

Pin No.

Name

Type

Description

J1-1,

J2-5

GND

PWR

Module Ground Supply Pins

J1-2

3V3OUT

Power

Input/

Output

3.3V output from integrated L.D.O. regulator. This pin is decoupled with a 100nF

capacitor to ground on the PCB module. The prime purpose of this pin is to provide

the 3.3V supply that can be used internally. For power supply configuration details

see Section 5.

J1-3

VCCIO

Power

Input

+1.8V to +3.3V supply to the UART Interface and CBUS I/O pins. For power supply

configuration details see Section 5.

J1-4

DCD#

Input

Data Carrier Detect Control Input.

J1-5

DSR#

Input

Data Set Ready Control Input / Handshake Signal.

J1-6

DTR#

Output

Data Terminal Ready Control Output / Handshake Signal.

J1-7

CTS#

Input

Clear To Send Control Input / Handshake Signal.

J1-8

RTS#

Output

Request to Send Control Output / Handshake Signal.

J1-9

RXD

Input

Receiving Asynchronous Data Input.

J1-10

TXD

Output

Transmit Asynchronous Data Output.

J2-1

SLD

GND

USB Cable Shield. Connected to GND via a 0ohm resistor.

J2-2

VBUS

Power

Output

5V Power output from the USB bus. For a low power USB bus powered design, up to

100mA can be sourced from the 5V supply and applied to the USB bus. A maximum

of 500mA can be sourced from the USB bus in a high power USB bus powered design.

Currents up to 1A can be sourced from a dedicated charger and applied to the USB

bus.

J2-3

VCC

Power

Input

5V power input for FT231X. For power supply configuration details see Section 5.

J2-4

RI#

Input

Ring Indicator Control Input. When remote wake up is enabled in the internal MTP

ROM taking RI# low >20ms can be used to resume the PC USB host controller from

suspend.

J2-6

RESET#

Input

FT231X active low reset line. Configured with an on board pull-up and recommended

filter capacitor. When no power is applied to the USB bus reset, will be held low, this

prevents current from flowing to the host or hub when in self-powered mode.

J2-7

CBUS3

I/O

Configurable CBUS I/O Pin. Function of this pin is configured in the device internal

MTP ROM. See CBUS Signal Options, Table 4.2.

J2-8

CBUS2

I/O

Configurable CBUS I/O Pin. Function of this pin is configured in the device internal

MTP ROM. See CBUS Signal Options,Table 4.2.

J2-9

CBUS1

I/O

Configurable CBUS I/O Pin. Function of this pin is configured in the device internal

MTP ROM. See CBUS Signal Options, Table 4.2.

J2-10

CBUS0

I/O

Configurable CBUS I/O Pin. Function of this pin is configured in the device internal

MTP ROM. See CBUS Signal Options,Table 4.2.

Table 4.1 – Module Pin Out Description