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STK11C68-C35I Datasheet(PDF) 3 Page - List of Unclassifed Manufacturers |
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STK11C68-C35I Datasheet(HTML) 3 Page - List of Unclassifed Manufacturers |
3 / 10 page STK11C68 June 1999 4-23 SRAM READ CYCLES #1 & #2 (VCC = 5.0V + 10%) b Note g: W must be high during SRAM READ cycles and low during SRAM WRITE cycles. Note h: I/O state assumes E, G < VIL and W > VIH; device is continuously selected. Note i: Measured ± 200mV from steady state output voltage. SRAM READ CYCLE #1: Address Controlledg, h SRAM READ CYCLE #2: E Controlledg NO. SYMBOLS PARAMETER STK11C68-20 STK11C68-25 STK11C68-35 STK11C68-45 UNITS #1, #2 Alt. MIN MAX MIN MAX MIN MAX MIN MAX 1tELQV tACS Chip Enable Access Time 20 25 35 45 ns 2tAVAV g tRC Read Cycle Time 20 25 35 45 ns 3tAVQV h tAA Address Access Time 22 25 35 45 ns 4tGLQV tOE Output Enable to Data Valid 8 10 15 20 ns 5tAXQX h tOH Output Hold after Address Change 5555 ns 6tELQX tLZ Chip Enable to Output Active 5555 ns 7tEHQZ i tHZ Chip Disable to Output Inactive 7 10 13 15 ns 8tGLQX tOLZ Output Enable to Output Active 0000 ns 9tGHQZ i tOHZ Output Disable to Output Inactive 7 10 13 15 ns 10 tELICCH f tPA Chip Enable to Power Active 0000 ns 11 tEHICCL e, f tPS Chip Disable to Power Standby 25 25 35 45 ns DATA VALID 5 tAXQX 3 tAVQV DQ (DATA OUT) ADDRESS 2 tAVAV 6 tELQX STANDBY DATA VALID 8 tGLQX 4 tGLQV DQ (DATA OUT) E ADDRESS 2 tAVAV G ICC ACTIVE 1 tELQV 10 tELICCH 11 tEHICCL 7 tEHQZ 9 tGHQZ |
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