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TMS320VC5416ZGU160 Datasheet(PDF) 10 Page - Texas Instruments |
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TMS320VC5416ZGU160 Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 98 page  www.ti.com 2 Introduction 2.1 Description 2.2 Pin Assignments 2.2.1 Terminal Assignments for the GGU Package A B D C E F H J L M K N G 1 2 3 4 5 6 7 8 10 12 11 13 9 TMS320VC5416 Fixed-Point Digital Signal Processor SPRS095O – MARCH 1999 – REVISED JANUARY 2005 This section describes the main features of the TMS320VC5416, lists the pin assignments, and describes the function of each pin. This data manual also provides a detailed description section, electrical specifications, parameter measurement information, and mechanical data about the available packaging. NOTE This data manual is designed to be used in conjunction with the TMS320C54x™ DSP Functional Overview (literature number SPRU307). The TMS320VC5416 fixed-point, digital signal processor (DSP) (hereafter referred to as the device unless otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction set. Separate program and data spaces allow simultaneous access to program instructions and data, providing a high degree of parallelism. Two read operations and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. The device also includes the control mechanisms to manage interrupts, repeated operations, and function calls. Figure 2-1 illustrates the ball locations for the 144-pin ball grid array (BGA) package and is used in conjunction with Table 2-1 to locate signal names and ball grid numbers. Figure 2-2 provides the pin assignments for the 144-pin low-profile quad flatpack (LQFP) package. Figure 2-1. 144-Ball GGU MicroStar BGA™ (Bottom View) 10 Introduction |
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