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USBN9603SLB Datasheet(PDF) 8 Page - National Semiconductor (TI) |
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USBN9603SLB Datasheet(HTML) 8 Page - National Semiconductor (TI) |
8 / 60 page 1.0 Signal/Pin Connection and Description (Continued) 8 www.national.com External Elements Choose C1 and C2 capacitors (see Figure 1) to match the crystal’s load capacitance. The load capacitance CL “seen” by the crystal is comprised of C1 in series with C2, and in parallel with the parasitic capacitance of the circuit. The parasitic capacitance is caused by the chip package, board layout and socket (if any), and can vary from 0 to 8 pF. The rule of thumb in choosing these capacitors is: CL = (C1*C2)/(C1+C2)+C Parasitic Figure 1. Typical Oscillator Circuit 1.2.3 USB Port 1.2.4 Microprocessor Interface Resistor R2 0 ΝΑ Capacitor C1 15 pF ±20% Capacitor C2 15 pF ±20% I/O Name Description I/O D+ USB D+ Upstream Port. This pin requires an external 1.5k pull-up to 3.3V to signal full speed operation. I/O D– USB D– Upstream Port I/O Name Description I MODE1-0 Interface Mode. Each of these pins should be hard-wired to VCC or GND to select the inter- face mode: MODE1-0 = 00. Mode 0: Non-multiplexed parallel interface mode MODE1-0 = 01. Mode 1: Multiplexed parallel interface mode MODE1-0 = 10. Mode 2: MICROWIRE interface mode MODE1-0 = 11. Mode 3: Reserved Note: Mode 3 also selects the MICROWIRE interface mode in the USBN9602, but this mode should be reserved to preserve compatibility with future devices. I DACK DMA Acknowledge. This active low signal is only used if DMA is enabled. If DMA is not used, this pin must be tied to VCC. O DRQ DMA Request. This pin is used for DMA request only if DMA is enabled. O INTR Interrupt. The interrupt signal modes (active high, active low or open drain) can be config- ured via the Main Control register. During reset, this signal is TRI-STATE. I CS Chip Select. Active low chip select I RD Read. Active low read strobe, parallel interface Component Parameters Values Tolerance XIN XOUT R1 R2 XTAL C2 C1 |
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Similar Description - USBN9603SLB |
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