TIMING DIAGRAM

*NOTE: The PSOK levels after the loss of the incoming DC source may be either 1.1V or 2.2V depending on the relative timing of the TDCPOK_OFF and TPWRP_GOOD_HOLD-Up

TIMING SPECIFICATIONS

Parameter

Description

Min

Max

Unit

Tsb_On

Delay from DC being applied to standby output being within regulation

0

3000

ms

Tsb_Vout

Delay from standby output to main output voltage being within regulation

50

500

ms

TPWR_GOOD_On

Delay from output voltages within regulation limits to PWR_GOOD assertion

20

500

ms

TVout_Hold-up

Delay from loss of AC to main output being out of regulation

1

ms

Tsb_Hold-up

Delay from loss of AC to standby output being out of regulation

20

2000

ms

TPWR_GOOD_OFF

Delay from de-assertion of PWR_GOOD to output falling out of regulation

1

ms

TPSON_On_Delay

Delay from PSON assertion to output being within regulation

300

500

ms

OUTPUT AND SIGNAL SPECIFICATION

Pin#

Function

Pin Type

Description

14-26, 39-51 RTN

Power Ground Power and Standby Return

1-13, 52-64 12V

Power

12V Output

37

12VSB

Power

12V Standby Output

38

PSINTERRUPT

Output

Active low; interrupt line for power

supply fault & warning detection as per

36

PRESENT#

Input

Power Supply Present Signal (shortest

35

PSOK*

Analog output

Combination of their power supply

output indicator signals:

1. DC input OK

2. Power Good

3. Power Supply Fault

34

ISHARE

Analog I/O

Analog representation of main output

current. Typical analog voltage shall be

60.15mV/Amp of main output current.

33

PSON#

Input

Power Supply on/off control signal

32

SCL

Input

SMBus/PMBus Clock

31

SDA

I/O

SMBus/PMBus Data

30

GND

Analog I/O

Power Supply Signal Ground

29

N/A

N/A

Reserved; no User connection

28

N/A

N/A

Reserved; no User connection

27

ADDR

Analog input PMBus Address