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TMS320C6713 Datasheet(PDF) 10 Page - Texas Instruments |
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TMS320C6713 Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 150 page  TMS320C6713, TMS320C6713B FLOATING-POINT DIGITAL SIGNAL PROCESSORS SPRS186I − DECEMBER 2001 − REVISED MAY 2004 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 device characteristics Table 2 provides an overview of the C6713/C6713B DSPs. The table shows significant features of the each device, including the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count. For more details on the C67x DSP device part numbers and part numbering, see Table 24 and Figure 12. Table 2. Characteristics of the C6713 and C6713B Processors HARDWARE FEATURES INTERNAL CLOCK SOURCE C6713/C6713B (FLOATING-POINT DSPs) HARDWARE FEATURES SOURCE GDP PYP Peripherals EMIF SYSCLK3 or ECLKIN 1 (32 bit) 1 (16 bit) Peripherals Not all peripheral pins are EDMA (16 Channels) CPU clock frequency 1 Not all peripheral pins are available at the same HPI (16 bit) SYSCLK2 1 available at the same time. (For more details, see the Device McASPs AUXCLK, SYSCLK2‡ 2 see the Device Configuration section.) I2Cs SYSCLK2 2 Configuration section.) P i hl f i McBSPs SYSCLK2 2 Peripheral performance is dependent on chip-level 32-Bit Timers 1/2 of SYSCLK2 2 dependent on chip-level configuration. GPIO Module SYSCLK2 1 Size (Bytes) 264K On-Chip Memory Organization 4K-Byte (4KB) L1 Program (L1P) Cache 4KB L1 Data (L1D) Cache 64KB Unified L2 Cache/Mapped RAM 192KB L2 Mapped RAM CPU ID+CPU Rev ID Control Status Register (CSR.[31:16]) 0x0203 BSDL File For the C6713/13B BSDL file, contact your Field Sales Representative. Frequency MHz 300, 225, 200 200, 167 Cycle Time ns 3.3 ns (C6713BGDP-300) 4.4 ns (C6713BGDP-225) 5 ns (C6713BGDPA-200) 4.4 ns (C6713GDP-225) 5 ns (C6713GDPA-200) 5 ns (C6713BPYP-200) 6 ns (C6713BPYPA-167) 5 ns (C6713PYP-200) 6 ns (C6713PYPA-167) Voltage Core (V) 1.20§ V (C6713/C6713B) 1.4 V (C6713B−300) 1.2 V Voltage I/O (V) 3.3 V Clock Generator Options Prescaler Multiplier Postscaler /1, /2, /3, ..., /32 x4, x5, x6, ..., x25 /1, /2, /3, ..., /32 27 x 27 mm 272-Ball BGA (GDP) − Packages 28 x 28 mm − 208-Pin PowerPAD PQFP (PYP) † PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. ‡ AUXCLK is the McASP internal high-frequency clock source for serial transfers. SYSCLK2 is the McASP system clock used for the clock check (high-frequency) circuit. § This value is compatible with existing 1.26V designs. C67x is a trademark of Texas Instruments. |
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