4Kx4 RAM
CY7C168A
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
February 3, 2000
Features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• High speed
—tAA = 15 ns
• Low active power
—633 mW
• Low standby power
—110 mW
• TTL-compatible inputs and outputs
•VIH of 2.2V
• Capable of withstanding greater than 2001V electrostat-
ic discharge
Functional Description
The CY7C168A is a high-performance CMOS static RAM or-
ganized as 4096 by 4 bits. Easy memory expansion is provided
by an active LOW Chip Enable (CE) and three-state drivers.
The CY7C168A has an automatic power-down feature, reduc-
ing the power consumption by 77% when deselected.
Writing to the device is accomplished when the Chip Select
(CE) and Write Enable (WE) inputs are both LOW. Data on the
four data input/output pins (I/O0 through I/O3) is written into the
memory location specified on the address pins (A0 through
A11).
Reading the device is accomplished by taking the Chip Enable
(CE) LOW, while Write Enable (WE) remains HIGH. Under
these conditions, the contents of the location specified on the
address pins will appear on the four data input/output pins
(I/O0 through I/O3).
The input/output pins remain in a high-impedance state when
Chip Enable (CE) is HIGH or Write Enable (WE) is LOW.
A die coat is used to insure alpha immunity.
Logic Block Diagram
Pin Configurations
128 x 128
ARRAY
C168A-1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
18
17
16
15
Top View
DIP/SOJ
7C168A
A1
A2
A3
A8 A9
A4
A0
COLUMN
DECODER
INPUTBUFFER
POWER
DOWN
WE
CE
I/O0
A 5
A 6
A 7
A 8
A 9
A11
WE
GND
CE
VCC
A 2
A 1
A 0
C168A-2
I/O1
A10A11
A5
A 4
I/O 0
I/O 1
I/O 2
I/O 3
I/O2
I/O3
A7
A6
A10
A3
(7C168A)
20
19
\
Selection Guide
7C168A-15
7C168A-20
7C168A-25
7C168A-35
7C168A-45
Maximum Access Time (ns)
15
20
25
35
45
Maximum Operating
Current (mA)
Commercial
115
90
90
90
90
Military
-
100
100
100
100
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