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ZN448E Datasheet(PDF) 5 Page - List of Unclassifed Manufacturers

Part # ZN448E
Description  8-BIT MICROPROCESSOR COMPATIBLE A-D CONVERTER
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ZN448E Datasheet(HTML) 5 Page - List of Unclassifed Manufacturers

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ZN448/9
5
If a free-running conversion is required, then the converter can
be made to cycle by inverting the
BUSY output and feeding it
to
WR. To ensure that the converter starts reliably after power-
up an initial start pulse is required. This can be ensured by
using a NOR gate instead of an inverter and feeding it with a
positive-going pulse which can be derived from a simple RC
network that gives a single pulse when power is applied, as
shown in Fig.4a.
The ADC will complete a conversion on every eighth clock
pulse, with the
BUSY output going high for a period
determined by the propagation delay of the NOR gate, during
which time the data can be stored in a latch. The time available
for storing data can be increased by inserting delays into the
inverter path.
A timing diagram for the continuous conversion mode is
shown in Fig.3b.
As the
BUSY output uses a passive pull-up the rise time of this
output depends on the RC time constant of the pull-up resistor
and load capacitance. In the continuous conversion mode the
use of a 4k7 external pull-up resistor is recommended to
reduce the risetime and ensure that a logic 1 level is reached.
Fig.4b Timing for continuous conversion
DATA OUTPUTS
The data outputs are provided with three-state buffers to allow
connection to a common data bus. An equivalent circuit is
shown in Fig.5.
Whilst the
RD input is high both output
transistors are turned off and the ZN448/9 presents only a high
impedance load to the bus.
When
RD is low the data outputs will assume the logic states
present at the outputs of the successive register.
A test circuit and timing diagram for the output enable/disable
delays are given in Fig.6.
Fig.4a Circuit for continuous conversion


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