CY7B923
CY7B933
10
Receiver Switching Characteristics Over the Operating Range[1]
Parameter
Description
7B933-155
7B933
7B933-400
Unit
Min.
Max
Min.
Max.
Min.
Max.
tCKR
Read Clock Period (No Serial Data Input), REFCLK
as Reference[15]
−1
+1
−1
+1
−1
+1
%
tB
Bit Time[16]
6.25
6.67
3.03
6.25
2.5
6.25
ns
tCPRH
Read Clock Pulse HIGH
5tB−3
5tB−3
5tB−3
ns
tCPRL
Read Clock Pulse LOW
5tB−3
5tB−3
5tB−3
ns
tRH
RDY Hold Time
tB−2.5
tB−2.5
tB−2.5
ns
tPRF
RDY Pulse Fall to CKR Rise
5tB−3
5tB−3
5tB−3
ns
tPRH
RDY Pulse Width HIGH
4tB−3
4tB−3
4tB−3
ns
tA
Data Access Time[17, 18]
2tB−2
2tB+
4
2tB−2
2tB+4
2tB−2
2tB+4
ns
tROH
Data Hold Time[17, 18]
tB−2.5
tB−2.5
tB−2.5
ns
tH
Data Hold Time from CKR Rise [17, 18]
2tB−3
2tB−3
2tB−3
ns
tCKX
REFCLK Clock Period Referenced to CKW of
Transmitter[19]
−0.1
+0.1
−0.1
+0.1
−0.1
+0.1
%
tCPXH
REFCLK Clock Pulse HIGH
6.5
6.5
6.5
ns
tCPXL
REFCLK Clock Pulse LOW
6.5
6.5
6.5
ns
tDS
Propagation Delay SI to SO (note PECL and TTL
thresholds)[20]
20
20
20
ns
tSA
Static Alignment[7, 21]
100
100
100
ps
tEFW
Error Free Window[7, 22]
0.9tB
0.9tB
0.9tB
Notes:
15. The period of tCKR will match the period of the transmitter CKW when the receiver is receiving serial data. When data is interrupted, CKR may drift to one of the range limits
above.
16. Receiver tB is calculated as tCKR/10 if no data is being received, or tCKW/10 if data is being received. See note.
17. Data includes Q0−7, SC/D, and RVS.
18. tA, tROH, and tH specifications are only valid if all outputs (CKR, RDY, Q0−7, SC/D, and RVS) are loaded with similar DC and AC loads.
19. REFCLK has no phase or frequency relationship with CKR and only acts as a centering reference to reduce clock synchronization time. REFCLK must be
within 0.1% of the transmitter CKW frequency, necessitating a
±500-PPM crystal.
20. The PECL switching threshold is the midpoint between the PECL
− V
OH, and VOL specification (approximately VCC − 1.35V). The TTL switching threshold is 1.5V.
21. Static alignment is a measure of the alignment of the Receiver sampling point to the center of a bit. Static alignment is measured by sliding one bit edge in
3,000 nominal transitions until a byte error occurs.
22. Error Free Window is a measure of the time window between bit centers where a transition may occur without causing a bit sampling error. EFW is measured
over the operating range, input jitter
< 50% Dj.
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