CY7C346
USE ULTRA37000TM FOR
ALL NEW DESIGNS
Document #: 38-03005 Rev. *B
Page 8 of 21
Commercial and Industrial External Asynchronous Switching Characteristics[6] Over Operating Range
Parameter
Description
7C346-25
7C346-30
7C346-35
Unit
Min.
Max.
Min.
Max.
Min.
Max.
tACO1
Asynchronous Clock Input to Output Delay[7]
25
30
35
ns
tACO2
Asynchronous Clock Input to Local Feedback to Combinatorial
Output[20]
39
46
55
ns
tAS1
Dedicated Input or Feedback Set-Up Time to Asynchronous
Clock Input[7]
5
6
8
ns
tAS2
I/O Input Set-Up Time to Asynchronous Clock Input[7]
19
22
28
ns
tAH
Input Hold Time from Asynchronous Clock Input[7]
6
8
10
ns
tAWH
Asynchronous Clock Input HIGH Time[7]
11
14
16
ns
tAWL
Asynchronous Clock Input LOW Time[7, 21]
9
11
14
ns
tACF
Asynchronous Clock to Local Feedback Input[4, 22]
15
18
22
ns
tAP
External Asynchronous Clock Period (1/(fMAXA4))
[4]
20
25
30
ns
fMAXA1
External Feedback Maximum Frequency in Asynchronous
Mode (1/(tACO1 + tAS1))
[4, 23]
33.3
27.7
23.2
MHz
fMAXA2
Maximum Internal Asynchronous Frequency[4, 24]
50
40
33.3
MHz
fMAXA3
Data Path Maximum Frequency in Asynchronous Mode[4, 25]
40
33.3
28.5
MHz
fMAXA4
Maximum Asynchronous Register Toggle Frequency 1/(tAWH
+ tAWL)
[4, 26]
50
40
33.3
MHz
tAOH
Output Data Stable Time from Asynchronous Clock Input[4, 27]
15
15
15
ns
Notes:
21. This parameter is measured with a positive-edge triggered clock at the register. For negative edge triggering, the tAWH and tAWL parameters must be swapped.
If a given input is used to clock multiple registers with both positive and negative polarity, tAWH should be used for both tAWH and tAWL.
22. This specification is a measure of the delay associated with the internal register feedback path for an asynchronous clock to LAB logic array input. This delay
plus the asynchronous register set-up time, tAS1, is the minimum internal period for an internal asynchronously clocked state machine configuration. This delay
is for feedback within the same LAB, assumes no expander logic in the clock path, and assumes that the clock input signal is applied to a dedicated input pin.
This parameter is tested periodically by sampling production material.
23. This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine configuration with external feedback can
operate. It is assumed that all data inputs, clock inputs, and feedback signals are applied to dedicated inputs and that no expander logic is employed in the clock
signal path or data path.
24. This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine with internal-only feedback can operate.
This parameter is determined by the lesser of (1/(tACF + tAS1)) or (1/(tAWH + tAWL)). If register output states must also control external points, this frequency can
still be observed as long as this frequency is less than 1/tACO1.
This specification assumes no expander logic is utilized, all data inputs and clock inputs are applied to dedicated inputs, and all state feedback is within a single
LAB. This parameter is tested periodically by sampling production material.
25. This frequency is the maximum frequency at which the device may operate in the asynchronously clocked data path mode. This specification is determined by
the lesser of 1/(tAWH + tAWL), 1/(tAS1 + tAH) or 1/tACO1. It assumes data and clock input signals are applied to dedicated input pins and no expander logic is used.
26. This specification indicates the guaranteed maximum frequency at which an individual output or buried register can be cycled in asynchronously clocked mode
by a clock signal applied to an external dedicated input pin.
27. This parameter indicates the minimum time that the previous register output data is maintained on the output after an asynchronous register clock input applied
to an external dedicated input pin.
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