Electronic Components Datasheet Search |
|
54LS192LMQB Datasheet(PDF) 3 Page - National Semiconductor (TI) |
|
|
54LS192LMQB Datasheet(HTML) 3 Page - National Semiconductor (TI) |
3 / 8 page Switching Characterisitcs VCC ea05V TA ea25 C (See Section 1 for waveforms and load configurations) RL e 2k Symbol Parameter CL e 15 pF Units Min Max fmax Maximum Count Frequency 30 MHz tPLH Propagation Delay 31 ns tPHL CPU or CPD to Qn 28 tPLH Propagation Delay 16 tPHL CPU to TCU 21 ns tPLH Propagation Delay 16 tPHL CPD to TCD 24 tPLH Propagation Delay 20 ns tPHL Pn to Qn 30 tPLH Propagation Delay 32 tPHL PL to Qn 30 ns tPHL Propagation Delay MR to Qn 25 Functional Description The ’192 is an asynchronously presettable decade and 4-bit binary synchronous updown (reversible) counter The op- erating modes of the ’192 decade counter and the ’193 bi- nary counter are identical with the only difference being the count sequences as noted in the State Diagram Each cir- cuit contains four masterslave flip-flops with internal gat- ing and steering logic to provide master reset individual pre- set count up and count down operations Each flip-flop contains JK feedback from slave to master such that a LOW-to-HIGH transition on its T input causes the slave and thus the Q output to change state Synchro- nous switching as opposed to ripple counting is achieved by driving the steering gates of all stages from a common Count Up line and a common Count Down line thereby causing all state changes to be initiated simultaneously A LOW-to-HIGH transition on the Count Up input will advance the count by one a similar transition on the Count Down input will decrease the count by one While counting with one clock input the other should be held HIGH Otherwise the circuit will either count by twos or not at all depending on the state of the first flip-flop which cannot toggle as long as either Clock input is LOW The Terminal Count Up (TCU) and Terminal Count Down (TCD) outputs are normally HIGH When a circuit has reached the maximum count state (9 for the ’192 15 for the ’193) the next HIGH-to-LOW transition of the Count Up Clock will cause TCU to go LOW TCU will stay LOW until CPU goes HIGH again thus effectively repeating the Count Up Clock but delayed by two gate delays Similarly the TCD output will go LOW when the circuit is in the zero state and the Count Down Clock goes LOW Since the TC outputs repeat the clock waveforms they can be used as the clock input signals to the next higher order circuit in a multistage counter TCU e Q0 Q3 CPU TCD e Q0 Q1 Q2 Q3 CPD Each circuit has an asynchronous parallel load capability permitting the counter to be reset When the Parallel Load (PL) and the Master Reset (MR) inputs are LOW informa- tion present on the Parallel Data inputs (P0 – P3) is loaded into the counter and appears on the outputs regardless of the conditions of the clock inputs A HIGH signal on the Master Reset input will disable the preset gates override both Clock inputs and latch each Q output in the LOW state If one of the Clock inputs is LOW during and after a reset or load operation the next LOW-to-HIGH transition of that Clock will be interpreted as a legitimate signal and will be counted State Diagram TLF10178 – 4 3 |
Similar Part No. - 54LS192LMQB |
|
Similar Description - 54LS192LMQB |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |