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XR16C854IJ Datasheet(PDF) 6 Page - Exar Corporation |
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XR16C854IJ Datasheet(HTML) 6 Page - Exar Corporation |
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6 / 51 page  XR16C854 6 Rev. 1.00P SYMBOL DESCRIPTION Symbol Pin Signal Pin Description 68 100 64 type UARTs (A-D) are enabled when the -CS pin is a logic 0. An individual UART channel is selected by the data contents of address bits A3-A4. When the 16 mode is selected (68/100 pin devices), this pin functions as -CSA, see definition under -CS A-B. This pin is not available on 64 pin packages which operate in the 16 mode only. -CS A-B 16,20 13,17 7,11 -CS C-D 50,54 64,68 38,42 I Chip Select A, B, C, D (active low) - This function is associated with the 16 mode only, and for individual chan- nels, A through D. When in 16 Mode, these pins enable data transfers between the user CPU and the XR16C854 for the channel(s) addressed. Individual UART sections (A, B, C, D) are addressed by providing a logic 0 on the respective -CS A-D pin. When the 68 mode is selected, the functions of these pins are reassigned. 68 mode functions are de- scribed under the their respective name/pin headings. -CSRDY - 76 - I Control Status Ready (active low) - This feature is available on 100 pin QFP packages only. On 100 pin packages, the Contents of the FIFORDY Register is read when this pin is a logic 0. However it should be noted, D0-D3 will contain the inverted logic states of TXRDY, status bits A-D, and D4-D7 the inverted logic states of RXRDY, status bits D4-D7. D0-D2 66-68 88-90 53-55 I/O D3-D7 1-5 91-95 56-60 Data Bus (Bi-directional) - These pins are the eight bit, three state data bus for transferring information to or from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive serial data stream. GND 6,23 96,20 14,28 GND 40,57 46,71 45,61 Pwr Signal and power ground. INT A-B 15,21 12,18 6,12 INT C-D 49,55 63,69 37,43 O Interrupt A, B, C, D (active high) - This function is associated with the 16 mode only. These pins provide individual channel interrupts, INT A-D. INT A-D are enabled when MCR bit-3 is set to a logic 1, interrupts are enabled in the interrupt enable register (IER), and when an interrupt con- |
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