CLK/2

OR

OUT-OF-RANGE

INDICATOR

OutV

OutEdge

DC_Coup

DCLK+

DCLK-

Data Bus Output

16 LVDS Pairs

1:2

DEMUX

8-BIT

ADC

FSR

CLK+

CLK-

2

Output

Clock

Generator

ADC081000

SNAS209G – FEBRUARY 2004 – REVISED MAY 2013

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Block Diagram

2

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