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66AK2H12AAAWA2 Datasheet(PDF) 10 Page - Texas Instruments |
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66AK2H12AAAWA2 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 354 page 66AK2H14/12/06 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SPRS866E—November 2012—Revised November 2013 List of Figures Figure 1-1 Functional Block Diagram for 66AK2H14 . . . . . .4 Figure 1-2 Functional Block Diagram for 66AK2H12 . . . . . .5 Figure 1-3 Functional Block Diagram for 66AK2H06 . . . . . .6 Figure 2-1 66AK2H14/12/06 Device Nomenclature . . . . . 18 Figure 3-1 C66x CorePac Block Diagram . . . . . . . . . . . . . . . 20 Figure 3-2 L1P Memory Configurations . . . . . . . . . . . . . . . . 21 Figure 3-3 L1D Memory Configurations . . . . . . . . . . . . . . . . 22 Figure 3-4 L2 Memory Configurations . . . . . . . . . . . . . . . . . 23 Figure 3-5 CorePac Revision ID Register (MM_REVID) . . . 26 Figure 4-1 66AK2H12 ARM CorePac Block Diagram . . . . . 27 Figure 4-2 66AK2H06 ARM CorePac Block Diagram . . . . . 28 Figure 4-3 ARM Interrupt Controller for Two Cortex-A15 Processor Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 4-4 ARM Interrupt Controller for Four Cortex-A15 Processor Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 5-1 AAW 1517-PIN BGA Package (Bottom View) . 33 Figure 5-2 Pin Map Panels (Bottom View) . . . . . . . . . . . . . . 33 Figure 5-3 66AK2H14/12/06 Pin Map Left Side Panel (A) — Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 5-4 66AK2H14/12/06 Pin Map Left Center Panel (B) — Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 5-5 66AK2H14/12/06 Pin Map Right Center Panel (C) — Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 5-6 66AK2H14/12/06 Pin Map Right Side Panel (D) — Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 6-1 Programmable Range n Start Address Register (PROGn_MPSAR) . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Figure 6-2 Programmable Range n End Address Register (PROGn_MPEAR) . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Figure 6-3 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPAR). . . 106 Figure 6-4 66AK2H14/12 Interrupt Topology . . . . . . . . . . 111 Figure 6-5 66AK2H06 Interrupt Topology . . . . . . . . . . . . . 112 Figure 7-1 TeraNet 3_A-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Figure 7-2 TeraNet 3_A-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Figure 7-3 TeraNet 3_C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Figure 7-4 TeraNet C66x to SDMA . . . . . . . . . . . . . . . . . . . . 193 Figure 7-5 TeraNet 3P_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Figure 7-6 TeraNet 3P_B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Figure 7-7 TeraNet 6P_B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Figure 7-8 TeraNet 3P_Tracer . . . . . . . . . . . . . . . . . . . . . . . . . 198 Figure 8-1 DEVSTAT Boot Mode Pins ROM Mapping . . . 206 Figure 8-2 Sleep Boot Mode Configuration Fields . . . . . 208 Figure 8-3 I2C Passive Mode Device Configuration Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Figure 8-4 I2C Master Mode Device Configuration Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Figure 8-5 SPI Device Configuration Fields . . . . . . . . . . . . 210 Figure 8-6 EMIF Boot Device Configuration Fields . . . . . 211 Figure 8-7 NAND Boot Device Configuration Fields. . . . 212 Figure 8-8 Serial Rapid I/O Boot Device Configuration Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Figure 8-9 Ethernet (SGMII) Boot Device Configuration Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Figure 8-10 PCIe Boot Device Configuration Fields . . . . . .216 Figure 8-11 HyperLink Boot Device Configuration Fields 217 Figure 8-12 UART Boot Mode Configuration Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218 Figure 8-13 Device Status Register. . . . . . . . . . . . . . . . . . . . . .234 Figure 8-14 Device Configuration Register (DEVCFG) . . . .235 Figure 8-15 JTAG ID (JTAGID) Register . . . . . . . . . . . . . . . . . .235 Figure 8-16 LRESETNMI PIN Status Register (LRSTNMIPINSTAT) . . . . . . . . . . . . . . . . . . . . . . . . .236 Figure 8-17 LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR) . . . . . . . . . . . . . . . . . . . .237 Figure 8-18 Reset Status Register (RESET_STAT) . . . . . . . . .238 Figure 8-19 Reset Status Clear Register (RESET_STAT_CLR) . . . . . . . . . . . . . . . . . . . . . . . . .239 Figure 8-20 Boot Complete Register (BOOTCOMPLETE). .239 Figure 8-21 Power State Control Register (PWRSTATECTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . .241 Figure 8-22 NMI Generation Register (NMIGRx) . . . . . . . . .242 Figure 8-23 IPC Generation Registers (IPCGRx) . . . . . . . . . .242 Figure 8-24 IPC Acknowledgement Registers (IPCARx) . .243 Figure 8-25 IPC Generation Registers (IPCGRH) . . . . . . . . . .244 Figure 8-26 IPC Acknowledgement Register (IPCARH) . . .244 Figure 8-27 Timer Input Selection Register (TINPSEL) . . . .245 Figure 8-28 Timer Output Selection Register (TOUTPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247 Figure 8-29 Reset Mux Register . . . . . . . . . . . . . . . . . . . . . . . . .249 Figure 8-30 Device Speed Register (DEVSPEED) . . . . . . . . .250 Figure 8-31 ARM Endian Configuration Register 0 (ARMENDIAN_CFGr_0), r=0..7. . . . . . . . . . . . . . .251 Figure 8-32 ARM Endian Configuration Register 1 (ARMENDIAN_CFGr_1), r=0..7. . . . . . . . . . . . . . .251 Figure 8-33 ARM Endian Configuration Register 2 (ARMENDIAN_CFGr_2), r=0..7. . . . . . . . . . . . . . .252 Figure 8-34 Chip Miscellaneous Control Register (CHIP_MISC_CTL0) . . . . . . . . . . . . . . . . . . . . . . . . .252 Figure 8-35 Chip Miscellaneous Control Register (CHIP_MISC_CTL1) . . . . . . . . . . . . . . . . . . . . . . . . .253 Figure 8-36 System Endian Status Register . . . . . . . . . . . . . .253 Figure 8-37 SYNECLK_PINCTL Register . . . . . . . . . . . . . . . . . .254 Figure 8-38 USB_PHY_CTL0 Register. . . . . . . . . . . . . . . . . . . .254 Figure 8-39 USB_PHY_CTL1 Register. . . . . . . . . . . . . . . . . . . .256 Figure 8-40 USB_PHY_CTL2 Register. . . . . . . . . . . . . . . . . . . .257 Figure 8-41 USB_PHY_CTL3 Register. . . . . . . . . . . . . . . . . . . .258 Figure 8-42 USB_PHY_CTL4 Register. . . . . . . . . . . . . . . . . . . .259 Figure 8-43 USB_PHY_CTL5 Register. . . . . . . . . . . . . . . . . . . .260 Figure 10-1 Core Before IO Power Sequencing . . . . . . . . . .270 Figure 10-2 IO-Before-Core Power Sequencing. . . . . . . . . .272 Figure 10-3 SmartReflex 4-Pin 6-bit VID Interface Timing275 Figure 10-4 RESETFULL Reset Timing . . . . . . . . . . . . . . . . . . .287 Figure 10-5 Soft/Hard Reset Timing. . . . . . . . . . . . . . . . . . . . .287 Figure 10-6 Boot Configuration Timing . . . . . . . . . . . . . . . . .288 Figure 10-7 Main PLL and PLL Controller . . . . . . . . . . . . . . . .289 Figure 10-8 PLL Secondary Control Register (SECCTL) . . .293 Figure 10-9 PLL Controller Divider Register (PLLDIVn) . . .294 |
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