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66AK2E05 Datasheet(PDF) 6 Page - Texas Instruments |
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66AK2E05 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 282 page  66AK2E05, 66AK2E02 SPRS865D – NOVEMBER 2012 – REVISED MARCH 2015 www.ti.com 3.8 Trademarks .......................................... 13 10.2 Recommended Operating Conditions ............. 205 3.9 Electrostatic Discharge Caution ..................... 13 10.3 Electrical Characteristics ........................... 206 3.10 Glossary ............................................. 13 10.4 Power Supply to Peripheral I/O Mapping .......... 207 4 C66x CorePac ........................................... 14 11 66AK2E0x Peripheral Information and Electrical Specifications ......................................... 208 4.1 Memory Architecture ................................ 15 11.1 Recommended Clock and Control Signal Transition 4.2 Memory Protection .................................. 18 Behavior ............................................ 208 4.3 Bandwidth Management ............................ 18 11.2 Power Supplies .................................... 208 4.4 Power-Down Control ................................ 19 11.3 Power Sleep Controller (PSC) ..................... 216 4.5 C66x CorePac Revision ............................. 20 11.4 Reset Controller .................................... 222 4.6 C66x CorePac Register Descriptions ............... 20 11.5 Core PLL (Main PLL), DDR3 PLL, NETCP PLL and 5 ARM CorePac ........................................... 21 the PLL Controllers ................................ 227 5.1 Features ............................................. 23 11.6 DDR3 PLL .......................................... 241 5.2 System Integration .................................. 23 11.7 NETCP PLL ........................................ 243 5.3 ARM Cortex-A15 Processor ......................... 23 11.8 External Interrupts ................................. 245 5.4 CFG Connection .................................... 25 11.9 DDR3 Memory Controller .......................... 245 5.5 Main TeraNet Connection ........................... 25 11.10 I2C Peripheral ..................................... 246 5.6 Clocking and Reset ................................. 26 11.11 SPI Peripheral .................................... 250 6 Terminals ................................................ 27 11.12 HyperLink Peripheral ............................. 253 6.1 Package Terminals .................................. 27 11.13 UART Peripheral ................................. 255 6.2 Pin Map ............................................. 27 11.14 PCIe Peripheral ................................... 256 6.3 Terminal Functions .................................. 32 11.15 Packet Accelerator ............................... 256 6.4 Pullup/Pulldown Resistors .......................... 59 11.16 Security Accelerator .............................. 257 7 Memory, Interrupts, and EDMA for 66AK2E0x ... 61 11.17 Network Coprocessor Gigabit Ethernet (GbE) Switch Subsystem ................................. 257 7.1 Memory Map Summary66AK2E0x .................. 61 11.18 SGMII/XFI Management Data Input/Output 7.2 Memory Protection Unit (MPU) for 66AK2E0x ...... 71 (MDIO) ............................................. 259 7.3 Interrupts for 66AK2E0x ............................. 84 11.19 Ten-Gigabit Ethernet (10GbE) Switch 7.4 Enhanced Direct Memory Access (EDMA3) Subsystem ......................................... 260 Controller ........................................... 129 11.20 Timers ............................................. 260 8 System Interconnect ................................. 140 11.21 General-Purpose Input/Output (GPIO) ........... 261 8.1 Internal Buses and Switch Fabrics ................ 140 11.22 Semaphore2 ...................................... 262 8.2 Switch Fabric Connections Matrix - Data Space .. 140 11.23 Universal Serial Bus 3.0 (USB 3.0) ............... 262 8.3 Switch Fabric Connections Matrix - Configuration 11.24 TSIP Peripheral ................................... 263 Space .............................................. 146 11.25 Universal Subscriber Identity Module (USIM) .... 265 8.4 Bus Priorities ....................................... 154 11.26 EMIF16 Peripheral ................................ 265 9 Device Boot and Configuration .................... 155 11.27 Emulation Features and Capability ............... 268 9.1 Device Boot ........................................ 155 11.28 Debug Port (EMUx) ............................... 271 9.2 Device Configuration ............................... 175 12 Mechanical Data ...................................... 278 10 Device Operating Conditions ...................... 204 12.1 Thermal Data ...................................... 278 10.1 Absolute Maximum Ratings ........................ 204 12.2 Packaging Information ............................. 278 6 Table of Contents Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2E05 66AK2E02 |
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