ADC10D1000CIUT datasheet(8/82 Pages) TI1

Part #	ADC10D1000CIUT

Description	Low Power, 10-Bit, Dual 1.0/1.5 GSPS or Single 2.0/3.0 GSPS ADC

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Manufacturer	TI1 [Texas Instruments]

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GND

VA

GND

VA

GND

VA

50 k:

VA

GND

VA

ADC10D1000, ADC10D1500

SNAS462Q – OCTOBER 2008 – REVISED MARCH 2013

www.ti.com

Table 4. Control and Status Balls (continued)

Ball No.

Name

Equivalent Circuit

Description

Calibration cycle initiate. The user can command

the device to execute a self-calibration cycle by

holding this input high a minimum of tCAL_H after

having held it low a minimum of tCAL_L. If this input

is held high at the time of power-on, the automatic

power-on calibration cycle is inhibited until this

D6

CAL

input is cycled low-then-high. This pin is active in

both ECM and Non-ECM. In ECM, this pin is

logically OR'd with the CAL Bit (Addr: 0h, Bit 15)

in the Control Register. Therefore, both pin and bit

must be set low and then either can be set high to

execute an on-command calibration.

Calibration Running indication. This output is

B5

CalRun

logic-high while the calibration sequence is

executing. This output is logic-low otherwise.

Power Down I- and Q-channel. Setting either input

to logic-high powers down the respective I- or Q-

channel. Setting either input to logic-low brings the

respective I- or Q-channel to a operational state

U3

PDI

after a finite time delay. This pin is active in both

V3

PDQ

ECM and Non-ECM. In ECM, each Pin is logically

OR'd with its respective Bit. Therefore, either this

pin or the PDI and PDQ Bit in the Control Register

can be used to power-down the I- and Q-channel

(Addr: 0h, Bit 11 and Bit 10), respectively.

Test Pattern Mode select. With this input at logic-

high, the device continuously outputs a fixed,

repetitive test pattern at the digital outputs. In the

A4

TPM

ECM, this input is ignored and the Test Pattern

Mode can only be activated through the Control

Register by the TPM Bit (Addr: 0h, Bit 12).

Non-Demuxed Mode select. Setting this input to

logic-high causes the digital output bus to be in

the 1:1 Non-Demuxed Mode. Setting this input to

A5

NDM

logic-low causes the digital output bus to be in the

1:2 Demuxed Mode. This feature is pin-controlled

only and remains active during ECM and Non-

ECM.

8

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