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ADC12DL065

SNAS249D – MARCH 2005 – REVISED APRIL 2013

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AC Electrical Characteristics

(1) (2) (3) (4)

Units

Parameter

Test Conditions

(Limits)

Maximum Clock Frequency

65

MHz (min)

Minimum Clock Frequency

15

MHz

Clock High Time

Duty Cycle Stabilizer On

7.7

3

ns (min)

Clock Low Time

Duty Cycle Stabilizer On

7.7

3

ns (min)

Clock Rise and Fall Times

Duty Cycle Stabilizer On

2

4

ns (max)

Clock High Time

Duty Cycle Stabilizer Off

7.7

6.2

ns (min)

Clock Low Time

Duty Cycle Stabilizer Off

7.7

6.2

ns (min)

Clock Rise and Fall Times

Duty Cycle Stabilizer Off

2

ns (max)

Conversion Latency

Parallel mode

7

Clock Cycles

3.5

ns (min)

Data Output Delay after Rising Clock

Parallel mode

6.0

Edge

9

ns (max)

Conversion Latency

Multiplex mode, Channel A

7.5

Clock Cycles

Conversion Latency

Multiplex mode, Channel B

8

Clock Cycles

3.5

ns (min)

Data Output Delay after Clock Edge

Multiplex mode

6.0

8

ns (max)

ABb to Data Skew

±0.5

ns (max)

Aperture Delay

2

ns

Aperture Jitter

1.2

ps rms

Data outputs into Hi-Z Mode

10

ns

Data Outputs Active after Hi-Z Mode

10

ns

1.0 µF on pins 4, 14; 0.1 µF on pins

Power Down Mode Exit Cycle

5,6,12,13; 10 µF between pins 5, 6 and

1

µs

between pins 12, 13

(1)

current is limited per Note 4 of the Absolute Maximum Ratings Table. However, errors in the A/D conversion can occur if the input goes

accurate conversions. See Figure 2.

(2)

(3)

(4)

(5)

Quality Level).

Figure 2.

10

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