ADC12L063

SNAS144E – JULY 2001 – REVISED MARCH 2013

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Specification Definitions

APERTURE DELAY is the time after the rising edge of the clock to when the input signal is acquired or held for

conversion.

APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample.

Aperture jitter manifests itself as noise in the output.

CONVERSION LATENCY See PIPELINE DELAY.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1

LSB

DUTY CYCLE s the ratio of the time that a repetitive digital waveform is high to the total time of one period. The

specification here refers to the ADC clock input signal.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise

and Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is

equivalent to a perfect ADC of this (ENOB) number of bits.

FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental

drops 3 dB below its low frequency value for a full scale input.

GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated as:

Gain Error = Positive Full Scale Error

− Offset Error

(1)

INTEGRAL NON LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from

negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last

code transition). The deviation of any given code from this straight line is measured from the center of that

code value.

INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two

sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the

power in the intermodulation products to the total power in the original frequencies. IMD is usually

expressed in dBFS.

MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC12L063 is ensured

not to have any missing codes.

IN

transition from negative full scale to the next code and its ideal value of 0.5 LSB.

IN

input voltage required to cause a transition from an output code 2047 to 2048.

OUTPUT DELAY is the time delay after the rising edge of the clock before the data update is presented at the

output pins.

PIPELINE DELAY (LATENCY) is the number of clock cycles between initiation of conversion and when that

data is presented to the output driver stage. Data for any given sample is available at the output pins the

Pipeline Delay plus the Output Delay after the sample is taken. New data is available at every clock cycle,

but the data lags the conversion by the pipeline delay.

POSITIVE FULL SCALE ERROR is the difference between the actual last code transition and its ideal value of

1½ LSB below positive full scale.

POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well the ADC rejects a change in the power

supply voltage. For the ADC12L063, PSRR1 is the ratio of the change in Full-Scale Error that results from

a change in the dc power supply voltage, expressed in dB. PSRR2 is a measure of how well an a. c.

signal riding upon the power supply is rejected at the output.

SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms

value of the sum of all other spectral components below one-half the sampling frequency, not including

harmonics or dc.

SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of

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