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ADC12J1600NKE Datasheet(PDF) 1 Page - Texas Instruments |
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ADC12J1600NKE Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 98 page  -100 -80 -60 -40 -20 0 0 225 450 675 900 1125 1350 Frequency (MHz) C001 Product Folder Sample & Buy Technical Documents Tools & Software Support & Community ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 ADC12Jxx00 12-Bit 1.6 or 2.7 GSPS ADCs With Integrated DDC 1 Features 2 Applications 1 • Excellent Noise and Linearity up to and beyond • Wireless Infrastructure FIN = 3 GHz • RF-Sampling Software Defined Radio • Configurable DDC • Wideband Microwave Backhaul • Decimation Factors from 4 to 32 (Complex • Military Communications Baseband Out) • SIGINT • Bypass Mode for Full Nyquist Output Bandwidth • RADAR and LIDAR • Usable Output Bandwidth of 540 MHz at • DOCSIS / Cable Infrastructure 4x Decimation and 2700 MSPS • Test and Measurement • Usable Output Bandwidth of 320 MHz at 4x Decimation and 1600 MSPS 3 Description • Usable Output Bandwidth of 67.5 MHz at The ADC12J1600 and ADC12J2700 devices are 32x Decimation and 2700 MSPS wideband sampling and digital tuning devices. Texas Instruments' giga-sample analog-to-digital converter • Usable Output Bandwidth of 40 MHz at (ADC) technology enables a large block of frequency 32x Decimation and 1600 MSPS spectrum to be sampled directly at RF. An integrated • Low Pin-Count JESD204B Subclass 1 Interface DDC (Digital Down Converter) provides digital filtering • Automatically Optimized Output Lane Count and down-conversion. The selected frequency block is made available on a JESD204B serial interface. • Embedded Low Latency Signal Range Indication Data is output as baseband 15-bit complex • Low Power Consumption information for ease of downstream processing. • Key Specifications Based on the digital down-converter (DDC) – Max Sampling Rate: 1600 or 2700 MSPS decimation and link output rate settings, this data is output on 1 to 5 lanes of the serial interface. – Min Sampling Rate: 1000 MSPS A DDC bypass mode allows the full rate 12-bit raw – DDC Output Word Size: 15-Bit Complex (30 ADC data to also be output. This mode of operation bits total) requires 8 lanes of serial output. – Bypass Output Word Size: 12-Bit Offset Binary The ADC12J1600 and ADC12J2700 devices are – Noise Floor: –147.3 dBFS/Hz (ADC12J2700) available in a 68-pin VQFN package. The device – Noise Floor: –145 dBFS/Hz (ADC12J1600) operates over the Industrial (–40°C ≤ TA ≤ 85°C) – IMD3: −64 dBc (FIN = 2140 MHz ± 30 MHz at ambient temperature range. −13 dBFS) Device Information(1) – FPBW (–3 dB): 3.2 GHz PART NUMBER PACKAGE BODY SIZE (NOM) – Peak NPR: 46 dB ADC12J1600 VQFN (68) 10.00 mm × 10.00 mm – Supply Voltages: 1.9 V and 1.2 V ADC12J2700 VQFN (68) 10.00 mm × 10.00 mm – Power Consumption (1) For all available packages, see the orderable addendum at – Bypass (2700 MSPS): 1.8 W the end of the datasheet. – Bypass (1600 MSPS): 1.6 W Bypass — Spectral Response – Power Down Mode: <50 mW ƒS = 2.7 GHz, FIN = 1897 MHz at –1 dBFS 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
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