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ADC12J1600NKET Datasheet(PDF) 6 Page - Texas Instruments |
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ADC12J1600NKET Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 98 page  VA19 AGND VA19 AGND V(CM_CLK) 50 50 1 k VA19 GND GND VA19 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com Pin Functions (continued) PIN EQUIVALENT CIRCUIT TYPE DESCRIPTION NAME NO. Serial Interface Clock This pin functions as the serial-interface clock input which clocks the serial data in SCLK 58 I and out. The Using the Serial Interface section describes the serial interface in more detail. Serial Data In SDI 57 I This pin functions as the serial-interface data input. The Using the Serial Interface section describes the serial interface in more detail. SYNC~ This pin provides the JESD204B-required synchronizing request input. A logic-low SYNC~ 30 I applied to this input initiates a lane alignment sequence. The choice of LVCMOS or differential SYNC~ is selected through bit 6 of the configuration register 0x202h. Connect this input to GND or VA19 if differential SYNC~ input is used. Serial Chip Select (active low) SCS 59 I This pin functions as the serial-interface chip select. The Using the Serial Interface section describes the serial interface in more detail. Serial Data Out SDO 56 O This pin functions as the serial-interface data output. The Using the Serial Interface section describes the serial interface in more detail. DIFFERENTIAL INPUT DEVCLK+ 15 Device Clock Input I The differential device clock signal must be AC coupled to these pins. The input DEVCLK– 16 signal is sampled on the rising edge of CLK. SYSREF+ 19 SYSREF The differential periodic waveform on these pins synchronizes the device per I JESD204B. If JESD204B subclass 1 synchronization is not required and these SYSREF– 20 inputs are not utilized they may be left unconnected. In that case ensure SysRef_Rcvr_En=0 and SysRef_Pr_En=0. SYNC~+/TMST+ 22 SYNC~/TMST This differential input provides the JESD204B-required synchronizing request input. A differential logic-low applied to these inputs initiates a lane alignment sequence. For differential SYNC~ usage, ensure that SYNC_DIFF_PD = 0 and SYNC_DIFFSEL = 1. I When the LVCMOS SYNC~ is selected these inputs can be used as the differential SYNC~-/TMST– 23 TIMESTAMP input. For TMST usage, ensure that SYNC_DIFF_PD = 0, SYNC_DIFFSEL = 0, and TIME_STAMP_EN = 1. For additional information see the Time Stamp section. These inputs may be left unconnected if they are not used for either the SYNC~ or TIMESTAMP functions. 6 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 |
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