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ADC14DS080 Datasheet(PDF) 10 Page - Texas Instruments |
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ADC14DS080 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 36 page VA AGND To Internal Circuitry I/O VA AGND To Internal Circuitry I/O ADC14DS080 SNAS428B – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com Timing and AC Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VDR = +3.0V, Internal VREF = +1.2V, fCLK = 80 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Timing measurements are taken at 50% of the signal amplitude. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (1) (2) Units Symb Parameter Conditions Typical (3) Limits (Limits) In Single-Lane Mode 65 Maximum Clock Frequency MHz (max) In Dual-Lane Mode 80 In Single-Lane Mode 25 Minimum Clock Frequency MHz (min) In Dual-Lane Mode 52.5 Single-Lane Mode 7.5 tCONV Conversion Latency Dual-Lane, Offset Mode 8 Clock Cycles Dual-Lane, Word Aligned Mode 9 tAD Aperture Delay 0.6 ns tAJ Aperture Jitter 0.1 ps rms (1) The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided current is limited per Absolute Maximum Ratings, Note 4. However, errors in the A/D conversion can occur if the input goes above 2.6V or below GND as described in the Operating Ratings section. (2) With a full scale differential input of 2VP-P , the 14-bit LSB is 122.1 µV. (3) Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical specifications are not ensured. LVDS Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VDR = +3.0V, Internal VREF = +1.2V, fCLK = 80 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Timing measurements are taken at 50% of the signal amplitude. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (1) (2) Units Symbol Parameter Conditions Typical (3) Limits (Limits) LVDS DC CHARACTERISTICS Output Differential Voltage 250 mV (min) VOD RL = 100Ω 350 (SDO+) - (SDO-) 450 mV (max) delta Output Differential Voltage Unbalance RL = 100Ω ±25 mV (max) VOD 1.125 V (min) VOS Offset Voltage RL = 100Ω 1.25 1.375 V (max) delta VOS Offset Voltage Unbalance RL = 100Ω ±25 mV (max) (1) The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided current is limited per Absolute Maximum Ratings, Note 4. However, errors in the A/D conversion can occur if the input goes above 2.6V or below GND as described in the Operating Ratings section. (2) With a full scale differential input of 2VP-P , the 14-bit LSB is 122.1 µV. (3) Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical specifications are not ensured. 10 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: ADC14DS080 |
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