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ADC14L040 Datasheet(PDF) 8 Page - Texas Instruments |
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ADC14L040 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 30 page  VA AGND To Internal Circuitry I/O ADC14L040 SNAS311B – JUNE 2005 – REVISED APRIL 2013 www.ti.com DC and Logic Electrical Characteristics (1)(2)(3) (continued) Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, External VREF = +1.0V, fCLK = 40 MHz, fIN = 20 MHz, tr = tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C Units Symbol Parameter Conditions Typical (4) Limits (4) (Limits) PD Pin = DGND 8 12 mA (max) ID Digital Supply Current PD Pin = VD , fCLK = 0 0 mA PD Pin = DGND, CL = 5 pF (5) 4 mA IDR Digital Output Supply Current PD Pin = VD, fCLK = 0 0 mA Total Power Consumption PD Pin = DGND, CL = 5 pF (6) 235 323 mW (max) Power Down Power Consumption PD Pin = VD, clock on 15 mW Rejection of Full-Scale Error with PSRR Power Supply Rejection Ratio 72 dB VA =3.0V vs. 3.6V (5) IDR is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins, the supply voltage, VDR, and the rate at which the outputs are switching (which is signal dependent). IDR=VDR(C0 x f0 + C1 x f1 +....C11 x f11) where VDR is the output driver power supply voltage, Cn is total capacitance on the output pin, and fn is the average frequency at which that pin is toggling. (6) Excludes IDR. See Note 5. AC Electrical Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, External VREF = +1.0V, fCLK = 40 MHz, fIN = 10 MHz, tr = tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C (1) (2) (3) (4) Units Symbol Parameter Conditions Typical(5) Limits(5) (Limits) fCLK1 Maximum Clock Frequency 40 MHz (min) fCLK2 Minimum Clock Frequency 5 MHz tCH Clock High Time Duty Cycle Stabilizer On 12.5 5 ns (min) tCL Clock Low Time Duty Cycle Stabilizer On 12.5 5 ns (min) tCH Clock High Time Duty Cycle Stabilizer Off 12.5 10 ns (min) tCL Clock Low Time Duty Cycle Stabilizer Off 12.5 10 ns (min) tCONV Conversion Latency 7 Clock Cycles Data Output Delay after Rising Clock tOD 6 9.6 ns (max) Edge tAD Aperture Delay 2 ns tAJ Aperture Jitter 0.7 ps rms 0.1 µF on pins 30, 31, 32; 10 µF between tPD Power Down Mode Exit Cycle 280 µs pins 30, 31 (1) The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided current is limited per Note 4 under Absolute Maximum Ratings. However, errors in the A/D conversion can occur if the input goes above VA or below GND by more than 100 mV. As an example, if VA is +3.3V, the full-scale input voltage must be ≤+3.4V to ensure accurate conversions. (2) To ensure accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin. (3) With the test condition for VREF = +1.0V (2VP-P differential input), the 14-bit LSB is 122.1 µV. (4) Timing specifications are tested at TTL logic levels, VIL = 0.4V for a falling edge and VIH = 2.4V for a rising edge. (5) Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing Quality Level). 8 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: ADC14L040 |
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