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ADC1175-50 Datasheet(PDF) 4 Page - Texas Instruments |
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ADC1175-50 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 27 page Dn DVDD DVSS 12 DVDD DVSS ADC1175-50 SNAS027G – JANUARY 2000 – REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS(1) (continued) Pin Symbol Equivalent Circuit Description No. 12 CMOS/TTL compatible digital clock input. VIN is sampled on CLK (10) the falling edge of CLK input. Conversion data digital Output pins. D0 is the LSB, D7 is the 3 thru 10 MSB. Valid data is output just after the rising edge of the D0–D7 (1 thru 8) CLK input. These pins are in a high impedance mode when the PD pin is low. Positive digital supply pin. Connect to a quiet voltage source of +5V. AVDD and DVDD should have a common source and 11, 13, 14 DVDD be separately bypassed with a 10 µF capacitor and a 0.1 µF (9, 11, 12) ceramic chip capacitor. See POWER SUPPLY CONSIDERATIONS for more information. 2, 24 The ground return for the digital supply. AVSS and DVSS DVSS (22, 24) should be connected together close to the ADC1175-50. Positive analog supply pin. Connect to a quiet voltage source of +5V. AVDD and DVDD should have a common source and 15, 18 AVDD be separately bypassed with a 10 µF capacitor and a 0.1 µF (13, 16) ceramic chip capacitor. See POWER SUPPLY CONSIDERATIONS for more information. The ground return for the analog supply. AVSS and DVSS 20, 21 AVSS should be connected together close to the ADC1175-50 (18, 19) package. 4 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC1175-50 |
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