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ADS5292IPFPR Datasheet(PDF) 1 Page - Texas Instruments |
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ADS5292IPFPR Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 67 page  ADS5292 www.ti.com SLAS788B – NOVEMBER 2011 – REVISED JULY 2012 Octal Channel 12-Bit, 80 MSPS and Low-Power ADC Check for Samples: ADS5292 1 FEATURES DESCRIPTION Using CMOS process technology and innovative • Maximum Sample Rate: 80 MSPS/12-Bit circuit techniques, the ADS5292 is a low power • High Signal-to-Noise Ratio 80MSPS 8-Channel ADC. Low power consumption, – 70-dBFS SNR at 5 MHz/80 MSPS high SNR, low SFDR, and consistent overload recovery allow users to design high performance – 71.5-dBFS SNR at 5 MHz/80 MSPS and systems. Decimation Filter = 2 The ADS5292 has a digital processing block that – 85-dBc SFDR at 5 MHz/80 MSPS integrates several commonly used digital functions for • Low Power Consumption improving system performance. It includes a digital – 48 mW/CH at 50 MSPS filter module that has built-in decimation filters (with – 54 mW/CH at 65 MSPS low-pass, high-pass and band-pass characteristics). The decimation rate is also programmable (by 2, by – 66 mW/CH at 80 MSPS (2 LVDS Wire Per 4, or by 8). This makes it useful for narrow-band Channel) applications, where the filters can be used • Digital Processing Block conveniently to improve SNR and knock-off – Programmable FIR Decimation Filter and harmonics, while at the same time reducing the output data rate. The device includes an averaging Oversampling to Minimize Harmonic mode where two channels (or even four channels) Interference can be averaged to improve SNR. – Programmable IIR High Pass Filter to Serial LVDS outputs reduce the number of interface Minimize DC Offset lines and enable the highest system integration. The – Programmable Digital Gain: 0 dB to 12 dB digital data from each channel ADC can be output – 2- or 4- Channel Averaging over one or two wires of LVDS output lines • Flexible Serialized LVDS Outputs: depending on the ADC sampling rate. This 2-wire interface helps keep the serial data rate low, allowing – One or Two wires of LVDS Output Lines per low cost FPGA based receivers to be used even at Channel Depending on ADC Sampling Rate high sample rate. A unique feature is the – Programmable Mapping Between ADC programmable mapping module that allows flexible Input Channels and LVDS Output Pins- mapping between the input channels and the LVDS Eases Board Design output pins. This helps greatly reduce the complexity of LVDS output routing and can potentially result in – Variety of Test Patterns to Verify Data cheaper system boards by reducing the number of Capture by FPGA/Receiver PCB layers. • Internal and External References The device integrates an internal reference trimmed • 1.8V Operation for Low Power Consumption to accurately match across devices. Best • Low-Frequency Noise Suppression performance is expected to be achieved through the • Recovery From 6-dB Overload within 1 Clock internal reference mode. The device can be driven with external references as well. Cycle • Package: 12-mm × 12-mm 80-Pin QFP The device is available in a 12 mm × 12 mm 80-pin QFP. It is specified over a –40°C to 85°C operating APPLICATIONS temperature range. ADS5292 is completely pin-to-pin and register compatible to ADS5294. • Ultrasound Imaging • Communication Applications • Multi-channel Data Acquisition 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2011–2012, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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