ADS7809

6

SBAS017C

www.ti.com

FIGURE 2. Serial Data Timing Using Internal Clock. (CS , EXT/INT and TAG Tied LOW.)

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

Convert Pulse Width

40

6000

ns

BUSY Delay

65

ns

BUSY LOW

8

µs

BUSY Delay After End of Conversion

220

ns

Aperture Delay

40

ns

Conversion Time

7.6

8

µs

Acquisition Time

2

µs

Throughput Time

9

10

µs

R/C LOW to DATACLK Delay

450

ns

DATACLK Period

440

ns

Data Valid to DATACLK HIGH Delay

20

75

ns

Data Valid After DATACLK LOW Delay

100

125

ns

External DATACLK

100

ns

External DATACLK HIGH

20

ns

External DATACLK LOW

30

ns

DATACLK HIGH Setup Time

20

ns

R/C to CS Setup Time

10

ns

SYNC Delay After DATACLK HIGH

15

35

ns

Data Valid Delay

25

55

ns

CS to Rising Edge Delay

25

ns

Data Available after CS LOW

6

µs

1

MSB Valid

R/C

DATACLK

SDATA

t

8

t

11

t

10

t

9

2

3

15

16

Bit 14 Valid

Bit 1 Valid

Bit 13 Valid

LSB Valid

t

2

t

3

BUSY

t

1