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ADC08D500 Datasheet(PDF) 8 Page - Texas Instruments

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Part # ADC08D500
Description  High Performance, Low Power, Dual 8-Bit, 500 MSPS A/D Converter
Download  48 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC08D500 Datasheet(HTML) 8 Page - Texas Instruments

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I / O
GND
V
A
TO INTERNAL
CIRCUITRY
ADC08D500
SNAS274F – MAY 2005 – REVISED APRIL 2013
www.ti.com
Operating Ratings
(1) (2) (continued)
VIN+, VIN- Voltage Range (Maintaining Common Mode)
0V to 2.15V
(100% duty cycle)
0V to 2.5V
(10% duty cycle)
Ground Difference
0V
(|GND - DR GND|)
CLK Pins Voltage Range
0V to VA
Differential CLK Amplitude
0.4VP-P to 2.0VP-P
Package Thermal Resistance
(1)
Package
θJA
θJC (Top of Package)
θJ-PAD (Thermal Pad)
128-Lead Exposed Pad
25°C / W
10°C / W
2.8°C / W
HLQFP
(1)
Soldering process must comply with TI’s Reflow Temperature Profile specifications. Refer to www.ti.com/packaging.
Converter Electrical Characteristics
The following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential
870mVP-P, CL = 10 pF, Differential, a.c. coupled Sinewave Input Clock, fCLK = 500 MHz at 0.5VP-P with 50% duty cycle, VBG =
Floating, Non-Extended Control Mode, SDR Mode, REXT = 3300Ω ±0.1%, Analog Signal Source Impedance = 100Ω
Differential. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25°C, unless otherwise noted.
(1) (2)
Typical
Limits
Units
Symbol
Parameter
Conditions
(3)
(3)
(Limits)
STATIC CONVERTER CHARACTERISTICS
DC Coupled, 1MHz Sine Wave Over
INL
Integral Non-Linearity
±0.3
±0.9
LSB (max)
ranged
DC Coupled, 1MHz Sine Wave Over
DNL
Differential Non-Linearity
±0.15
±0.6
LSB (max)
ranged
Resolution with No Missing Codes
8
Bits
−1.5
LSB (min)
VOFF
Offset Error
-0.45
0.5
LSB (max)
VOFF_ADJ Input Offset Adjustment Range
Extended Control Mode
±45
mV
PFSE
Positive Full-Scale Error (4)
−0.6
±25
mV (max)
NFSE
Negative Full-Scale Error (4)
−1.31
±25
mV (max)
FS_ADJ
Full-Scale Adjustment Range
Extended Control Mode
±20
±15
%FS
NORMAL MODE (non DES) DYNAMIC CONVERTER CHARACTERISTICS
FPBW
Full Power Bandwidth
Normal (non DES) Mode
1.7
GHz
(1)
The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this
device.
(2)
To ensure accuracy, it is required that VA and VDR be well bypassed. Each supply pin must be decoupled with separate bypass
capacitors. Additionally, achieving rated performance requires that the backside exposed pad be well grounded.
(3)
Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing
Quality Level).
(4)
Calculation of Full-Scale Error for this device assumes that the actual reference voltage is exactly its nominal value. Full-Scale Error for
this device, therefore, is a combination of Full-Scale Error and Reference Voltage Error. See Figure 2. For relationship between Gain
Error and Full-Scale Error, see Specification Definitions for Gain Error.
8
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Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: ADC08D500


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