SCL

SDA

t

LOW

t

R

t

F

t

HDSTA

t

HDSTA

t

HDDAT

t

BUF

t

SUDAT

t

HIGH

t

SUSTA

t

SUSTO

P

S

S

P

6

ADS1015-Q1

SBAS511A – JULY 2010 – REVISED MARCH 2016

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Product Folder Links: ADS1015-Q1

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Copyright © 2010–2016, Texas Instruments Incorporated

Electrical Characteristics (continued)

All specifications at –40°C to +125°C, VDD = 3.3 V, and Full-Scale (FS) = ±2.048 V, unless otherwise noted. Typical values

are at 25°C.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL INPUT/OUTPUT

High logic-level input voltage

0.7 VDD

5.5

V

Low logic-level input voltage

GND – 0.5

0.3 VDD

V

Low logic-level output

voltage

GND

0.15

0.4

V

High-level input leakage

10

μA

Low-level input leakage

10

μA

7.6 I

FAST MODE

HIGH-SPEED MODE

UNIT

MIN

MAX

MIN

MAX

SCL operating frequency

0.01

0.4

0.01

3.4

MHz

Bus free time between START and STOP

condition

600

160

ns

Hold time after repeated START condition.

After this period, the first clock is generated.

600

160

ns

Repeated START condition setup time

600

160

ns

Stop condition setup time

600

160

ns

Data hold time

0

0

ns

Data setup time

100

10

ns

SCL clock low period

1300

160

ns

SCL clock high period

600

60

ns

Clock/data fall time

300

160

ns

Clock/data rise time

300

160

ns