ADS831

3

SBAS087A

ADS831E

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

CMOS Compatible

Rising Edge of Convert Clock

CMOS/TTL Compatible

Straight Offset Binary

DIGITAL INPUTS

Logic Family

Convert Command

Start Conversion

100

µA

10

µA

High Level Input Voltage

+3.5

V

Low Level Input Voltage

+1.0

V

Input Capacitance

5pF

DIGITAL OUTPUTS

Logic Family

Logic Coding

VDRV = 5V

+0.1

V

+0.2

V

+4.9

V

+4.8

V

VDRV = 3V

+0.1

V

+2.8

V

Output Capacitance

5pF

ACCURACY (Internal Reference, 2Vp-p, Unless Otherwise Noted)

Zero Error (Referred to –FS)

at 25

°C

–2.5

±0.5

+2.5

%FS

Zero Error Drift (Referred to –FS)

±53

ppm/

°C

at 25

°C

–2.5

±0.5

+2.5

%FS

±75

ppm/

°C

Power Supply Rejection of Gain

∆ V

55

dB

Internal REFT Tolerance

Deviation from Ideal 3.0V

±10

±100

mV

Internal REFB Tolerance

Deviation from Ideal 2.0V

±10

±100

mV

External REFT Voltage Range

REFB + 0.8

3.0

V

External REFB Voltage Range

1.25

2.0

REFT – 0.8

V

Reference Input Resistance

REFT to REFB

800

Ω

POWER SUPPLY REQUIREMENTS

Operating

+4.75

+5.0

+5.25

V

Operating

58

70

mA

Power Dissipation: VDRV = 5V

External Reference

290

350

mW

VDRV = 3V

External Reference

275

mW

VDRV = 5V

Internal Reference

310

mW

VDRV = 3V

Internal Reference

285

mW

Thermal Resistance,

θ

JA

SSOP-20

115

°C/W

NOTES: (1) Spurious Free Dynamic Range refers to the magnitude of the largest harmonic. (2) dBFS means dB relative to Full Scale. (3) Two-tone

intermodulation distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the two-tone fundamental

envelope. (4) Effective number of bits (ENOB) is defined by (SINAD – 1.76) /6.02. (5) A 50k

Ω pull-down resistor is inserted internally. (6) Excludes internal

reference.