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ADS7842EB Datasheet(PDF) 10 Page - Texas Instruments |
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ADS7842EB Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 20 page  ADS7842 SBAS103C 10 www.ti.com STARTING A CONVERSION A conversion is initiated on the falling edge of the WR input, with valid signals on A0, A1, and CS . The ADS7842 will enter the conversion mode on the first rising edge of the external clock following the WR pin going LOW. The ADS7842 will start the conversion on the 1st clock cycle. The MSB will be approximated by the Capacitive Digital-to-Analog Con- verter (CDAC) on the 1st clock cycle, the 2nd-MSB on the 2nd cycle, and so on until the LSB has been decided on the 12th clock cycle. The BUSY output will go LOW 20ns after the falling edge of the WR pin. The BUSY output will return HIGH just after the ADS7842 has finished a conversion and the data will be valid on pins 7-13, 15-19. The rising edge of BUSY can be used to latch the data. It is recommended that the data be read immediately after each conversion. The switching noise of the asynchronous data transfer can cause digital feedthrough degrading the converter’s performance. See Figure 2. READING DATA Data from the ADS7842 will appear at pins 7-13 and 15-19. The MSB will output on pin 7 while the LSB will output on pin 19. The outputs are coded in Straight Binary (with 0V = 000H and VREF = FFFH, see Table IV). Following a conversion, the BUSY pin will go HIGH. After BUSY goes HIGH, the CS and RD pins may be brought LOW to enable the 12-bit output bus. CS and RD must be held LOW for at least 25ns seconds following BUSY HIGH. Data will be valid 25ns seconds after the falling edge of both CS and RD. The output data will remain valid for 25ns seconds following the rising edge of both CS and RD. See Figure 4 for the read cycle timing diagram. POWER-DOWN MODE The ADS7842 incorporates a unique method of placing the ADC in the power-down mode. Rather than adding an extra pin to the package, the A0 address pin is used in conjunction with the RD pin to place the device in power-down mode and also to ‘wake-up’ the ADC following power-down. In this shutdown mode, all analog and digital circuitry is turned off. The simplest way to place the ADS7842 in power-down mode is immediately following a conversion. After a conver- sion has been completed and the BUSY output has returned HIGH, CS and RD must be brought LOW for a minimum of 25ns. While keeping CS LOW, RD is brought HIGH and the ADS7842 enters the power-down mode, provided the A0 pin is HIGH (see Figure 5 and Table III). In order to ‘wake-up’ the device following power-down, A0 must be LOW when RD switches from LOW to HIGH a second time (see Figure 6). The typical supply current of the ADS7842 with a 5V supply and 200kHz sampling rate is 550 µA. In the power-down mode the current is typically reduced to 3 µA. SYMBOL DESCRIPTION MIN TYP MAX UNITS tCONV Conversion Time 6.5 µs tACQ Acquisition Time 1.5 µs tCKP Clock Period 500 ns tCKL Clock LOW 150 ns tCKH Clock HIGH 150 ns t1 CS to WR/RD Setup Time 0 ns t2 Address to CS Hold Time 0 ns t3 CS LOW 25 ns t4 CLK to WR Setup Time 25 ns t5 CS to BUSY LOW 20 ns t6 CLK to WR LOW 5 ns t7 CLK to WR HIGH 25 ns t8 WR to CLK HIGH 25 ns t9 Address Hold Time 5 ns t10 Address Setup Time 5 ns t11 BUSY to RD Delay 0 ns t12 CLK LOW to BUSY HIGH 10 ns t13 BUS Access 25 ns t14 BUS Relinquish 25 ns t15 Address to RD HIGH 2 ns t16 Address Hold Time 2 ns t17 RD HIGH to CLK LOW 50 ns TABLE II. Timing Specifications (+VCC = +4.75V to +5.25V, TA = –40°C to +85°C, CLOAD = 50pF). TABLE I. Timing Specifications (+VCC = +2.7V to 3.6V, TA = –40°C to +85°C, CLOAD = 50pF). SYMBOL DESCRIPTION MIN TYP MAX UNITS tCONV Conversion Time 3.5 µs tACQ Acquisition Time 1.5 µs tCKP Clock Period 300 ns tCKL Clock LOW 150 ns tCKH Clock HIGH 150 ns t1 CS to WR/RD Setup Time 0 ns t2 Address to CS Hold Time 0 ns t3 CS LOW 25 ns t4 CLK to WR Setup Time 25 ns t5 CS to BUSY LOW 20 ns t6 CLK to WR LOW 5 ns t7 CLK to WR HIGH 25 ns t8 WR to CLK HIGH 25 ns t9 Address Hold Time 5 ns t10 Address Setup Time 5 ns t11 BUSY to RD Delay 0 ns t12 CLK LOW to BUSY HIGH 10 ns t13 BUS Access 25 ns t14 BUS Relinquish 25 ns t15 Address to RD HIGH 2 ns t16 Address Hold Time 2 ns t17 RD HIGH to CLK LOW 50 ns |
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