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TPS3808G25DBVT Datasheet(PDF) 6 Page - Texas Instruments |
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TPS3808G25DBVT Datasheet(HTML) 6 Page - Texas Instruments |
6 / 32 page TPS3808 SBVS050K – MAY 2004 – REVISED OCTOBER 2015 www.ti.com 7.5 Electrical Characteristics 1.7 V ≤ VDD ≤ 6.5 V, RLRESET = 100 kΩ, CLRESET = 50 pF, over operating temperature range (TJ = –40°C to 125°C), unless otherwise noted. Typical values are at TJ = 25°C (1). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT –40°C < TJ < 125°C 1.7 6.5 V VDD Input supply range 0°C < TJ < 85°C 1.65 6.5 V VDD = 3.3 V, RESET not asserted 2.4 5 MR, RESET, CT open IDD Supply current (current into VDD pin) μA VDD = 6.5 V, RESET not asserted 2.7 6 MR, RESET, CT open 1.3 V ≤ VDD < 1.8 V, IOL = 0.4 mA 0.3 VOL Low-level output voltage 1.8 V ≤ VDD ≤ 6.5 V, IOL = 1 mA 0.4 V VPOR Power-up reset voltage(2) VOL (max) = 0.2 V, IRESET = 15 μA 0.8 TPS3808G01 –2% ±1% 2% VIT ≤ 3.3 V –1.5% ±0.5% 1.5% Negative-going input VIT 3.3 V < VIT ≤ 5.0 V –2% ±1% 2% threshold accuracy VIT ≤ 3.3 V –40°C < TJ < 85°C –1.25% ±0.5% 1.25% 3.3 V < VIT ≤ 5.0 V –40°C < TJ < 85°C –1.5% ±0.5% 1.5% TPS3808G01 1.5% 3% VHYS Hysteresis on VIT pin VIT Fixed versions 1% 2.5% RMR MR Internal pullup resistance 70 90 k Ω TPS3808G01 VSENSE = VIT –25 25 nA Input current at ISENSE SENSE pin Fixed versions VSENSE = 6.5 V 1.7 μA IOH RESET leakage current VRESET = 6.5 V, RESET not asserted 300 nA CT pin VIN = 0 V to VDD 5 Input capacitance, CIN pF any pin Other pins VIN = 0 V to 6.5 V 5 VIL MR logic low input 0 0.3 VDD V VIH MR logic high input 0.7 VDD VDD (1) RLRESET and CLRESET are the resistor and capacitor connected to the RESET pin. (2) The lowest supply voltage (VDD) at which RESET becomes active. Trise(VDD) ≥ 15 μs/V. 6 Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: TPS3808 |
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