Electronic Components Datasheet Search |
|
BQ2014H Datasheet(PDF) 10 Page - Texas Instruments |
|
|
BQ2014H Datasheet(HTML) 10 Page - Texas Instruments |
10 / 28 page The return-to-one data bit frame consists of three dis- tinct sections: 1. The first section is used to start the transmission by either the host or the bq2014H taking the HDQ pin to a logic-low state for a period, tSTRH;B. 2. The next section is the actual data transmission, where the data should be valid by a period, tDSU;B, after the negative edge used to start communica- tion. The data should be held for a period, tDH;DV, to allow the host or bq2014H to sample the data bit. 3. The final section is used to stop the transmission by returning the HDQ pin to a logic-high state by at least a period, tSSU;B, after the negative edge used to start communication. The final logic-high state should be until a period tCYCH;B, to allow time to en- sure that the bit transmission was stopped prop- erly. The timings for data and break communication are given in the serial communication timing speci- fication and illustration sections. Communication with the bq2014H is always performed with the bit transmitted first. Figure 5 shows an example of a communication sequence to read the bq2014H NACH register. bq2014H Command Code and Registers The bq2014H status registers are listed in Table 8 and de- scribed below. All registers are Read/Write in the bq2014H. Caution: When writing to bq2014H registers ensure that proper data are written. A write-verify read is recommended. Command Code The bq2014H latches the command code when eight valid command bits have been received by the bq2014H. The command code contains two fields: I W/R bit I Command address The W/R bit of the command code is used to select whether the received command is for a read or a write function: The W/R values are Command Code Bits 76 5 4 3 2 1 0 W/R - -- - - - - where W/R is 0 The bq2014H outputs the requested regis- ter contents specified by the address por- tion of command code. 1 The following eight bits should be written to the register specified by the address por- tion of command code. The lower 7-bit field of the command code contains the address portion of the register to be accessed: Command Code Bits 76 5 4 3 2 1 0 - AD6 AD5 AD4 AD3 AD2 AD1 AD0 (LSB) Primary Status Flags Register (FLGS1) The FLGS1 register (address = 01h) contains the pri- mary bq2014H flags. The charge status flag (CHGS) is asserted when a valid charge rate is detected. Charge rate is deemed valid when VSRO >VSRQ.A VSRO of less than VSRQ or discharge activity clears CHGS. The CHGS values are FLGS1 Bits 76 5 4 3 2 1 0 CHGS - -- - - - - where CHGS is 0 Either discharge activity detected or VSRO ≤ VSRQ 1VSRO >VSRQ The battery replaced flag (BRP) is asserted whenever the bq2014H is reset either by application of VCC or by a serial port command. BRP is reset when either a valid charge action increments NAC to be equal to LMD, or a valid charge action is detected after the EDV1 flag is as- serted. BRP = 1 signifies that the device has been reset. The BRP values are FLGS1 Bits 76 5 4 3 2 1 0 - BRP - - - - - - where BRP is 0 Battery is charged until NAC = LMD or dis- charged until the EDV1 flag is asserted 1 bq2014H is reset 4-10 bq2014H |
Similar Part No. - BQ2014H |
|
Similar Description - BQ2014H |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |