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BQ24157SYFFR Datasheet(PDF) 6 Page - Texas Instruments |
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BQ24157SYFFR Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 45 page  Not Recommended for New Designs bq24157S SLUSB76B – FEBRUARY 2013 – REVISED MAY 2015 www.ti.com Electrical Characteristics (continued) Circuit of Figure 28, VBUS = 5 V, HZ_MODE = 0, OPA_MODE = 0 (CD = 0), TJ = –40°C to 125°C, TJ = 25°C for typical values (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT CURRENT LIMITING TJ = 0°C to 125°C 88 93 98 IIN = 100 mA mA TJ = –40°C to 125°C 86 93 98 IIN_LIMIT Input current limiting threshold TJ = 0°C to 125°C 450 475 500 IIN = 500 mA mA TJ = –40°C to 125°C 440 475 500 VREF BIAS REGULATOR VBUS > VIN(min) or V(CSOUT) > VBUS(min), VREF Internal bias regulator voltage 2 6.5 V I(VREF) = 1 mA, C(VREF) = 1 μF VREF output short current limit 30 mA BATTERY RECHARGE THRESHOLD V(RCH) Recharge threshold voltage Below V(OREG) 100 120 150 mV V(SCOUT) decreasing below threshold, Deglitch time 130 ms tFALL = 100 ns, 10-mV overdrive STAT OUTPUTS Low-level output saturation voltage, STAT pin IO = 10 mA, sink current 0.55 V VOL(STAT) High-level leakage current for STAT Voltage on STAT pin is 5 V 1 μA I2C BUS LOGIC LEVELS AND TIMING CHARACTERISTICS VOL Output low threshold level IO = 10 mA, sink current 0.4 V VIL Input low threshold level V(pullup) = 1.8 V, SDA and SCL 0.4 V VIH Input high threshold level V(pullup) = 1.8 V, SDA and SCL 1.2 V I(BIAS) Input bias current V(pullup) = 1.8 V, SDA and SCL 1 μA f(SCL) SCL clock frequency 3.4 MHz BATTERY DETECTION Battery detection current before charge done Begins after termination detected, I(DETECT) –0.5 mA (sink current) (2) V(CSOUT) ≤ V(OREG) tDETECT Battery detection time 262 ms SLEEP COMPARATOR Sleep-mode entry threshold, V(SLP) 2.3 V ≤ V(CSOUT) ≤ V(OREG), VBUS falling 0 40 100 mV VBUS – VCSOUT V(SLP_EXIT) Sleep-mode exit hysteresis 2.3 V ≤ V(CSOUT) ≤ V(OREG) 140 200 260 mV Deglitch time for VBUS rising above V(SLP) + Rising voltage, 2-mV overdrive, tRISE = 100 ns 30 ms V(SLP_EXIT) UNDERVOLTAGE LOCKOUT (UVLO) UVLO IC active threshold voltage VBUS rising – exits UVLO 3.05 3.3 3.55 V UVLO(HYS) IC active hysteresis VBUS falling below UVLO – enters UVLO 120 150 mV Power up delay 140 ms PWM Voltage from BOOT pin to SW pin During charge or boost operation 6.5 V Internal top reverse blocking MOSFET on- IIN(LIMIT) = 500 mA, measured from VBUS to PMID 180 250 resistance Internal top N-channel switching MOSFET on- Measured from PMID to SW, 120 250 m Ω resistance VBOOT – VSW= 4 V Internal bottom N-channel MOSFET on- Measured from SW to PGND 110 210 resistance f(OSC) Oscillator frequency 3.0 MHz Frequency accuracy –10% 10% D(MAX) Maximum duty cycle 99.5% D(MIN) Minimum duty cycle 0 Synchronous mode to non-synchronous mode Low-side MOSFET cycle-by-cycle current sensing 100 mA transition current threshold(2) (2) Bottom N-channel FET always turns on for approximately 30 ns, and then turns off if current is too low. 6 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: bq24157S |
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