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AMC1305L25DWR Datasheet(PDF) 5 Page - Texas Instruments

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Part # AMC1305L25DWR
Description  AMC1305x High-Precision, Reinforced Isolated Delta-Sigma Modulators
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

AMC1305L25DWR Datasheet(HTML) 5 Page - Texas Instruments

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AMC1305L25, AMC1305M05, AMC1305M25
www.ti.com
SBAS654C – JUNE 2014 – REVISED DECEMBER 2014
8.6 IEC Safety Limiting Values
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output (I/O) circuitry. A
failure of the I/O circuitry can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient
power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures.
The safety-limiting constraint is the operating virtual junction temperature range specified in the Absolute Maximum Ratings
table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware
determine the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of
a device installed in the JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages and
is conservative. The power is the recommended maximum input voltage times the current. The junction temperature is then
the ambient temperature plus the power times the junction-to-air thermal resistance.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IS
Safety input, output, or supply current
θJA = 80.2°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C
90
mA
TC
Maximum case temperature
150
°C
8.7 IEC 61000-4-5 Ratings
PARAMETER
TEST CONDITIONS
VALUE
UNIT
VIOSM
Surge immunity
1.2-µs rise time / 50-
μs fall time, voltage surge
±10000
V
8.8 Isolation Characteristics
PARAMETER
TEST CONDITIONS
AMC1305
UNIT
AC voltage
1000
VRMS
VIORM
Maximum working insulation voltage
DC voltage
1500
VDC
t = 1 s (100% production test),
VPD(t)
Partial discharge test voltage
3977
VPEAK
partial discharge < 5 pC
t = 60 s (qualification test)
7000
VPEAK
VIOTM
Transient overvoltage
t = 1 s (100% production test)
8400
VPEAK
RIO
Isolation resistance
VIO = 500 V
>109
8.9 Package Characteristics
(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
L(I01)
Minimum air gap (clearance)
Shortest pin to pin distance through air
8
mm
Minimum external tracking
Shortest pin to pin distance across the package
L(I02)
8
mm
(creepage)
surface
Tracking resistance
CTI
DIN IEC 60112/VDE 0303 part 1
400
V
(comparative tracking index)
Distance through the double insulation
Minimum internal gap
0.027
mm
(internal clearance)
(2 x 0.0135 mm)
PD
Pollution degree
2
Degrees
Barrier capacitance input to
CIO
VI = 0.8 VPP at 1 MHz
1.2
pF
output
(1)
Apply the creepage and clearance requirements according to the specific equipment isolation standards of a specific application. Care
must be taken to maintain the creepage and clearance distance of the board design to ensure that the mounting pads of the isolator on
the printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal according to the
measurement techniques illustrated in the Isolation Glossary section. Techniques such as inserting grooves or ribs on the PCB are used
to help increase these specifications.
Copyright © 2014, Texas Instruments Incorporated
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