bq24740

Table 1. TERMINAL FUNCTIONS – 28-PIN QFN

TERMINAL

DESCRIPTION

NAME

NO.

CHGEN

1

Charge enable active-low logic input. LO enables charge. HI disables charge.

Adapter current sense resistor, negative input. A 0.1-

µF ceramic capacitor is placed from ACN pin to AGND for

ACN

2

common-mode filtering. A 0.1-

µF ceramic capacitor is placed from ACN to ACP to provide differential-mode filtering.

Adapter current sense resistor, positive input. A 0.1-

µF ceramic capacitor is placed from ACN to ACP to provide

ACP

3

differential-mode filtering. A 0.1-

µF ceramic capacitor is placed from ACP pin to AGND for common-mode filtering.

Low power mode detect active-high open-drain logic output. Place a 10-k

Ω pullup resistor from LPMD pin to the

pullup-voltage rail. Place a positive-feedback resistor from LPMD pin to LPREF pin for programming hysteresis (see

LPMD

4

output is LO when IADAPT pin voltage is higher than LPREF pin voltage.

Adapter detected voltage set input. Program the adapter detect threshold by connecting a resistor divider from

adapter input to ACDET pin to AGND pin. Adapter voltage is detected if ACDET-pin voltage is greater than 2.4 V.

ACDET

5

overvoltage protection; it disables charge when ACDET > 3.1 V. ACOV does not latch, and normal operation

resumes when ACDET < 3.1 V.

Adapter current set input. The voltage ratio of ACSET voltage versus VDAC voltage programs the input current

regulation set-point during Dynamic Power Management (DPM). Program by connecting a resistor divider from VDAC

ACSET

6

to ACSET to AGND; or by connecting the output of an external DAC to the ACSET pin and connect the DAC supply

to the VDAC pin.

Low power voltage set input. Connect a resistor divider from VREF to LPREF and AGND to program the reference

for the LOPWR comparator. The LPREF-pin voltage is compared to the IADAPT-pin voltage and the logic output is

LPREF

7

given on the LPMD open-drain pin. Connecting a positive-feedback resistor from LPREF pin to LPMD pin programs

the hysteresis.

Logic low turns off the Input Current Sense Amplifier (IADAPT) when adapter is not detected and ACDET pin is < 0.6

IADSLP

8

V - allows lower battery discharge current. Logic high keeps IADAPT current-sense amplifier on when adapter is not

detected and ACDET pin is <0.6 V - this allows measuring battery discharge current.

Analog ground. Ground connection for low-current sensitive analog and digital signals. On PCB layout, connect to the

AGND

9

analog ground plane, and only connect to PGND through the PowerPad underneath the IC.

3.3-V regulated voltage output. Place a 1-

µF ceramic capacitor from VREF to AGND pin close to the IC. This voltage

VREF

10

could be used for ratiometric programming of voltage and current regulation. VREF is the source for the internal

circuit.

Charge voltage set reference input. Connect the VREF or external DAC voltage source to the VDAC pin. Battery

voltage, charge current, and input current are programmed as a ratio of the VDAC pin voltage versus the VADJ,

VDAC

11

SRSET, and ACSET pin voltages, respectively. Place resistor dividers from VDAC to VADJ, SRSET, and ACSET

pins to AGND for programming. A DAC could be used by connecting the DAC supply to VDAC and connecting the

output to VADJ, SRSET, or ACSET.

Charge voltage set input. The voltage ratio of VADJ voltage versus VDAC voltage programs the battery voltage

regulation set-point. Program by connecting a resistor divider from VDAC to VADJ, to AGND; or, by connecting the

VADJ

12

output of an external DAC to VADJ, and connect the DAC supply to VDAC. VADJ connected to REGN programs the

default of 4.2 V per cell.

Valid adapter active-low detect logic open-drain output. Pulled low when input voltage is above ACDET programmed

EXTPWR

13

threshold, OR input current is greater than 1.25 A with 10-m

Ω sense resistor. Connect a 10-kΩ pullup resistor from

EXTPWR pin to pullup supply rail.

Synchronous mode current set input. Place a resistor from ISYNSET to AGND to program the charge undercurrent

ISYNSET

14

threshold to force non-synchronous converter operation at low output current, and to prevent negative inductor

current. Threshold should be set at greater than half of the maximum inductor ripple current (50% duty cycle).

Adapter current sense amplifier output. IADAPT voltage is 20 times the differential voltage across ACP-ACN. Place a

IADAPT

15

100-pF or less ceramic decoupling capacitor from IADAPT to AGND.

Charge current set input. The voltage ratio of SRSET voltage versus VDAC voltage programs the charge current

SRSET

16

regulation set-point. Program by connecting a resistor divider from VDAC to SRSET to AGND; or by connecting the

output of an external DAC to SRSET pin and connect the DAC supply to VDAC pin.

Battery voltage remote sense. Directly connect a kelvin sense trace from the battery pack positive terminal to the

BAT

17

BAT pin to accurately sense the battery pack voltage. Place a 0.1-

µF capacitor from BAT to AGND close to the IC to

filter high-frequency noise.

Charge current sense resistor, negative input. A 0.1-

µF ceramic capacitor is placed from SRN to SRP to provide

SRN

18

differential-mode filtering. An optional 0.1-

µF ceramic capacitor is placed from SRN pin to AGND for common-mode

filtering.

Charge current sense resistor, positive input. A 0.1-

µF ceramic capacitor is placed from SRN to SRP to provide

SRP

19

differential-mode filtering. A 0.1-

µF ceramic capacitor is placed from SRP pin to AGND for common-mode filtering.

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