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BQ27542DRZT-G1 Datasheet(PDF) 8 Page - Texas Instruments |
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BQ27542DRZT-G1 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 38 page tSU(STA) SCL SDA tw(H) tw(L) tf tr t(BUF) tr td(STA) REPEATED START th(DAT) tsu(DAT) tf tsu(STOP) STOP START bq27542-G1 SLUSC33 – APRIL 2015 www.ti.com 8.14 Timing Requirements: I 2C-Compatible Interface TA = –40°C to 85°C, CREG = 0.47μF, 2.45 V < VREGIN = VBAT < 5.5 V; typical values at TA = 25°C and VREGIN = VBAT = 3.6 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT tr SCL/SDA rise time 300 ns tf SCL/SDA fall time 300 ns tw(H) SCL pulse width (high) 600 ns tw(L) SCL pulse width (low) 1.3 μs tsu(STA) Setup for repeated start 600 ns td(STA) Start to first falling edge of SCL 600 ns tsu(DAT) Data setup time 1000 ns th(DAT) Data hold time 0 ns tsu(STOP) Setup time for stop 600 ns tBUF Bus free time between stop and start 66 μs fSCL Clock frequency 400 kHz Figure 2. I2C-Compatible Interface Timing Diagrams 8 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq27542-G1 |
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