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DP8344B Datasheet(PDF) 11 Page - National Semiconductor (TI) |
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DP8344B Datasheet(HTML) 11 Page - National Semiconductor (TI) |
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11 / 184 page  10 Communications Processor Introduction (Continued) 14 DATA FLOW The CPU registers are all dual port that is they have sepa- rate input and output paths This arrangement allows a sin- gle register to function as both a source and a destination within the same instruction Figures 1-6a through 1-6f show the internal data flow path for the BCP The CPU registers are a central element to this path When a register functions as an output its contents are placed on the Source bus When a register is an input data from the Destination bus is written into that register The other key element in the data path is the ALU This unit does all of the arithmetic and data manipulation operations but it also has bus multiplexing capabilities Both the Data Memory bus and a portion of the Instruction Memory bus are routed to this unit and serve as alternative sources of data Since the data flow is always through this unit most data moves may include arithmetic manipulations with no penalty in execution time Figure 1-6a shows the data path for all arithmetic instruc- tions and register to register moves The source register contents are placed on the Source bus routed through the TLF9336 – C3 TLF9336 – C4 TLF9336 – C5 FIGURE 1-6a Register to Register FIGURE 1-6b Data Memory WRITE FIGURE 1-6c Data Memory READ TLF9336 – C6 TLF9336 – C7 TLF9336 – C8 FIGURE 1-6d WRITE to Transmitter FIGURE 1-6e READ from Receiver FIGURE 1-6f Load Immediate Data 11 |
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