74ALVC74 datasheet(2/20 Pages) PHILIPS

Part #	74ALVC74

Description	Dual D-type flip-flop with set and reset; positive-edge trigger

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Manufacturer	PHILIPS [NXP Semiconductors]

Direct Link	http://www.nxp.com

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2 / 20 page

2003 May 26

2

Philips Semiconductors

Product speciﬁcation

Dual D-type ﬂip-ﬂop with set and reset;

positive-edge trigger

74ALVC74

FEATURES

• Wide supply voltage range from 1.65 to 3.6 V

• Complies with JEDEC standard:

JESD8-7 (1.65 to 1.95 V)

JESD8-5 (2.3 to 2.7 V)

JESD8B/JESD36 (2.7 to 3.6 V).

• 3.6 V tolerant inputs/outputs

• CMOS low power consumption

• Direct interface with TTL levels (2.7 to 3.6 V)

• Power-down mode

• Latch-up performance exceeds 250 mA

• ESD protection:

HBM EIA/JESD22-A114-A exceeds 2000 V

MM EIA/JESD22-A115-A exceeds 200 V.

DESCRIPTION

The 74ALVC74 is a dual positive-edge triggered, D-type

flip-flop with individual data (D), clock (CP), set (SD) and

reset (RD) inputs and complementary Q and Q outputs.

The set and reset are asynchronous active LOW inputs

and operate independently of the clock input. Information

on the data input is transferred to the Q output on the

LOW-to-HIGH transition of the clock pulse. The D inputs

must be stable one set-up time prior to the LOW-to-HIGH

clock transition for predictable operation.

Schmitt-trigger action in the clock input makes the circuit

highly tolerant to slower clock rise and fall times.

QUICK REFERENCE DATA

GND = 0 V; Tamb =25 °C.

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW).

PD =CPD × VCC2 × fi × N+ Σ(CL × VCC2 × fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VCC = supply voltage in Volts;

N = total load switching outputs;

Σ(CL × VCC2 × fo) = sum of the outputs.

2. The condition is VI = GND to VCC.

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

tPHL/tPLH

propagation delay nCP to nQ, nQVCC = 1.8 V; CL = 30 pF; RL =1kΩ

3.7

ns

VCC = 2.5 V; CL = 30 pF; RL = 500 Ω

2.6

ns

VCC = 2.7 V; CL = 50 pF; RL = 500 Ω

2.8

ns

VCC = 3.3 V; CL = 50 pF; RL = 500 Ω

2.7

ns

tPHL/tPLH

propagation delay nSD, nRD to nQ, nQVCC = 1.8 V; CL = 30 pF; RL =1kΩ

3.5

ns

VCC = 2.5 V; CL = 30 pF; RL = 500 Ω

2.5

ns

VCC = 2.7 V; CL = 50 pF; RL = 500 Ω

3.1

ns

VCC = 3.3 V; CL = 50 pF; RL = 500 Ω

2.3

ns

fmax

maximum clock frequency

425

MHz

CI

input capacitance

3.5

pF

CPD

power dissipation capacitance per buffer

VCC = 3.3 V; notes 1 and 2

35

pF

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