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74LVC1G126DRLRG4 Datasheet(PDF) 10 Page - Texas Instruments |
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74LVC1G126DRLRG4 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 30 page A Y OE 1 2 4 SN74LVC1G126 SCES224R – APRIL 1999 – REVISED JANUARY 2015 www.ti.com 9 Detailed Description 9.1 Overview The SN74LVC1G126 device contains a dual buffer gate with output enable control and performs the Boolean function Y = A. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pull- down resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. 9.2 Functional Block Diagram 9.3 Feature Description • 1.65 V to 5.5 V operating voltage range • Allows down voltage translation – 5 V to 3.3 V – 5 V or 3.3 V to 1.8 V • Inputs accept voltages to 5.5 V – 5.5-V tolerance on input pin when VCC = 0 V • Ioff feature – Allows voltage on the inputs and outputs when VCC is 0 V – Able to reduce leakage when VCC is 0 V 9.4 Device Functional Modes Table 1. Function Table INPUTS OUTPUT Y OE A H H H H L L L X Z 10 Submit Documentation Feedback Copyright © 1999–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC1G126 |
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