CD54AC112, CD74AC112

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS

WITH CLEAR AND PRESET

SCHS325 – JANUARY 2003

2

POST OFFICE BOX 655303

FUNCTION TABLE

(each flip-flop)

INPUTS

OUTPUTS

PRE

CLR

CLK

J

K

Q

Q

L

H

X

X

X

H

L

H

LX

X

X

L

H

L

LX

X

X

H†

H†

H

H

↓

LL

Q0

Q0

H

H

↓

HL

H

L

H

H

↓

LHL

H

H

H

↓

H

H

Toggle

H

H

H

X

X

Q0

Q0

† Output states are unpredictable if PRE and CLR go high

simultaneously after both being low at the same time.

logic diagram (positive logic)

PRE

CLK

K

Q

Q

CLR

J

–0.5 V to 6 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±20 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±100 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance,

67

°C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

M package

73

°C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65

°C to 150°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51-7.